A statistical static timing analysis considering correlations between delays

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 353-358

  Tsukiyama, S ^a   Tanaka, M ^b   Fukui, M ^b  

^a CHUO UNIVERSITY   (Japan)

^b PANASONIC CORPORATION   (Japan)

Author keywords

Algorithm design and analysis; CMOS logic circuits; Delay; Gaussian distribution; Logic gates; Semiconductor device modeling; Signal analysis; Stochastic processes; Switching circuits; Timing

Indexed keywords

ALGORITHMS; CHOPPERS (CIRCUITS); COMBINATORIAL CIRCUITS; COMBINATORIAL MATHEMATICS; COMBINATORIAL SWITCHING; COMPUTER AIDED DESIGN; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; GAUSSIAN DISTRIBUTION; GRAPH THEORY; LOGIC DESIGN; LOGIC GATES; NORMAL DISTRIBUTION; RANDOM PROCESSES; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; SIGNAL ANALYSIS; STOCHASTIC MODELS; STOCHASTIC SYSTEMS; SWITCHING CIRCUITS; TIMING CIRCUITS; TIMING DEVICES;

ALGORITHM DESIGN AND ANALYSIS; CMOS LOGIC CIRCUITS; DELAY; STATISTICAL STATIC TIMING ANALYSIS; STOCHASTIC VARIABLE; SWITCHING DELAY; TIME COMPLEXITY; TIMING;

LOGIC CIRCUITS;

EID: 84949778735     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913332     Document Type: Conference Paper

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