Performance optimization method by gate sizing using statistical static timing analysis

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2000, Pages 111-116

  Hashimoto, Masanori ^a   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); LSI CIRCUITS; STATISTICAL METHODS;

GATE SIZING; STATISTICAL STATIC TIMING ANALYSIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033720722     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)