CAD issues for CMOS VLSI design in SOI

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 105-110

  Shepard, Kenneth L ^a,b  

^a Columbia University ^*  (United States)

^b CadMOS Design Technlogy   (Costa Rica)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT DESIGN; TIMING CIRCUITS; VLSI CIRCUITS;

CIRCUIT LEVELS; FLOATING BODIES; INITIAL CONDITIONS; RECENT PROGRESS; STATIC NOISE ANALYSIS; STATIC TIMING ANALYSIS; SWITCHING ACTIVITIES; TRANSISTOR LEVEL;

COMPUTER AIDED DESIGN;

EID: 84949959065     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915213     Document Type: Conference Paper

References (19)

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