|
|
Volumn , Issue , 2000, Pages 239-242
|
|
Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology
a
a
Columbia Univ
*
(United States)
|
|
Author keywords
[No Author keywords available]
|
|
Indexed keywords
BIPOLAR TRANSISTORS;
COMPUTER AIDED ANALYSIS;
COMPUTER SIMULATION;
DIGITAL INTEGRATED CIRCUITS;
FIELD EFFECT TRANSISTORS;
LEAKAGE CURRENTS;
SILICON ON INSULATOR TECHNOLOGY;
THRESHOLD VOLTAGE;
PARTIALLY DEPLETED SILICON ON INSULATOR TECHNOLOGY;
STATIC NOISE ANALYSIS;
SPURIOUS SIGNAL NOISE;
|
|
EID: 0033684557
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/337292.337403 Document Type: Conference Paper |
|
Times cited : (5)
|
|
References (12)
|
