Improved alternative wiring scheme applying dominator relationship

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 473-478

  Sze, Chin Ngai ^a   Wu, Yu Liang ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Automatic test pattern generation; Circuit optimization; Circuit synthesis; Computer science; Delay; Field programmable gate arrays; Logic; Random access memory; Wire; Wiring

Indexed keywords

ALGORITHMS; AUTOMATIC TEST PATTERN GENERATION; COMPUTER AIDED DESIGN; COMPUTER SCIENCE; ELECTRIC WIRING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC SYNTHESIS; OPTIMIZATION; RANDOM ACCESS STORAGE; REDUNDANCY; TREES (MATHEMATICS); WIRE;

CIRCUIT OPTIMIZATION; CIRCUIT SYNTHESIS; DELAY; LOGIC; RANDOM ACCESS MEMORY;

LOGIC CIRCUITS;

EID: 84949796149     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913353     Document Type: Conference Paper

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