Layout analysis to extract open nets caused by systematic failure mechanisms

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 367-372

  Chakravarty, S ^a   Komeyli, K ^a   Savage, E W ^a   Carruthers, M J ^a   Stastny, B T ^a   Zachariah, S T ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Abstracts; Algorithm design and analysis; Aluminum; Bridge circuits; Circuit faults; Circuit testing; Contacts; Copper; Failure analysis; FETs

Indexed keywords

ABSTRACTING; ALGORITHMS; ALUMINUM; BRIDGE CIRCUITS; CONTACTS (FLUID MECHANICS); COPPER; ELECTRIC NETWORK ANALYSIS; FAILURE (MECHANICAL); VLSI CIRCUITS;

ALGORITHM DESIGN AND ANALYSIS; CIRCUIT FAULTS; CIRCUIT TESTING; FETS; LAYOUT ANALYSIS; OPEN DEFECTS; RANDOM PARTICLES; SYSTEMATIC FAILURE;

FAILURE ANALYSIS;

EID: 84948443065     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011166     Document Type: Conference Paper

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