Integrated approach for circuit and fault extraction of VLSI circuits

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1996, Pages 96-104

  Goncalves, F M ^a   Teixeira, I C ^a   Teixeira, J P ^a  

^a INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC FAULT CURRENTS; GEOMETRY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

VERY LARGE SCALE INTEGRATION CIRCUITS FAULT EXTRACTION; VIRTUAL TEST ENVIRONMENT;

VLSI CIRCUITS;

EID: 0030412371     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)