A novel algorithm for multi-node bridge analysis of large VLSI circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 333-338

  Zachariah, S T ^a   Chakravarty, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BRIDGE CIRCUITS; COMPUTATION THEORY; FAILURE ANALYSIS; PARAMETER ESTIMATION;

DEFECT BASED TESTING (DBT);

VLSI CIRCUITS;

EID: 0035011619     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)