Hierarchical clustered register file organization for VLIW processors

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

Volumn , Issue , 2003, Pages

  Zalamea, Javier ^a   Llosa, Josep ^a   Ayguadé, Eduard ^a   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED PARAMETER NETWORKS; FILE ORGANIZATION; PARALLEL PROCESSING SYSTEMS; SCHEDULING;

CLUSTER SELECTION; COMMUNICATION OPERATION; DESIGN EXPLORATION; INSTRUCTION SCHEDULING; INTERCLUSTER COMMUNICATION; MICROPROCESSOR DESIGNS; REGISTER ALLOCATION; REGISTER FILE ORGANIZATIONS;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84947286374     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2003.1213178     Document Type: Conference Paper

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