Partitioned schedules for clustered VLIW architectures

Proceedings of the International Parallel Processing Symposium, IPPS

Volumn , Issue , 1998, Pages 386-391

  Fernandes, Marcio Merino ^a   Llosa, Josep ^a   Topham, Nigel ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; COMPUTER SYSTEMS PROGRAMMING; FILE ORGANIZATION; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; STORAGE ALLOCATION (COMPUTER);

CLUSTERED VERY LONG INSTRUCTION WORD (VLIW) ARCHITECTURES; MODULO SCHEDULING; SOFTWARE PIPELINING;

PARALLEL PROCESSING SYSTEMS;

EID: 0031650008     PISSN: 10637133     EISSN: None     Source Type: None    
DOI: 10.1109/IPPS.1998.669945     Document Type: Conference Paper

References (17)

1. M. Aloqeely C. Chen A new technique for exploiting regularity in data path synthesis EURO-DAC'94, European Design Automation Conference EURO-DAC'94, European Design Automation Conference 1994
2. M. Berry D. Chen P. Koss D. Kuck The perfect club benchmarks: Effective performance evaluation of supercomputers 1988 Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign
3. A. Capitanio N. Dutt A. Nicolau Partitioned register files for VLIWs: A preliminary analysis of trade-offs Proceedings of the MICRO-25-The 25th Annual International Symposium on Microarchitecture Proceedings of the MICRO-25-The 25th Annual International Symposium on Microarchitecture 1992
4. A. Charlesworth An approach to scientific array processing: The architectural design of the AP120B/FPS-164 family Computer 14 9 1981
5. J. Dongarra R. Hinds Unrolling loops in Fortran Software-Practice and Experience 219 226 1979
6. M. Fernandes J. Llosa N. Topham Allocating lifetimes to queues in software pipelined architectures EUROPAR'97, Third International Euro-Par Conference EUROPAR'97, Third International Euro-Par Conference Passau Germany 1997
7. M. Fernandes J. Llosa N. Topham Extending a VLIW architecture model 1997 ECS-CSG-34-97 Edinburgh University, Department of Computer Science
8. M. Fernandes J. Llosa N. Topham Using queues for register file organization in VLIW architectures 1997 ECS-CSG-29-97 Edinburgh University, Department of Computer Science
9. J. Fisher Very long instruction word architectures and the ELI-512 Proceedings of the 10th Annual International Symposium on Computer Architecture Proceedings of the 10th Annual International Symposium on Computer Architecture 1983
10. S. Gerez E. Woutersen Assignment of storage values to sequential read-write memories EURO-DAC'96, European Design Automation Conference EURO-DAC'96, European Design Automation Conference 1996
11. A. Heubi M. Ansorge F. Pellandini A low power VLSI architecture with an application to adaptive algorithms for digital hearing aids EUSIPCO-94, Seventh European Signal Processing Conference EUSIPCO-94, Seventh European Signal Processing Conference 1994
12. J. Janssen H. Corporaal Partitioned register file for TTAs Proceedings of the MICRO-28-The 28th Annual International Symposium on Microarchitecture Proceedings of the MICRO-28-The 28th Annual International Symposium on Microarchitecture 1995
13. D. Lavery W. Hwu Unrolling-based optimizations for modulo scheduling Proceedings of the MICRO-28-The 28th Annual International Symposium on Microarchitecture Proceedings of the MICRO-28-The 28th Annual International Symposium on Microarchitecture 1995
14. J. Llosa M. Valero E. Ayguadé J. Labarta Register requirements of pipelined loops and their effect on performance 2nd International Workshop on Massive Parallelism: Hardware, Software and Applications 2nd International Workshop on Massive Parallelism: Hardware, Software and Applications 1994
15. B. Rau Iterative modulo scheduling The International Journal of Parallel Processing February 1996
16. B. Rau C. Glaeser Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing 14th Annual Workshop on Microprogramming 14th Annual Workshop on Microprogramming 1981
17. B. Rau D. Yen W. Yen R. Towle The Cydra 5 departmental supercomputer Computer January 1989