Independent-gate controlled asymmetrical SRAM cells in double-gate MOSFET technology for improved READ stability

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn , Issue , 2006, Pages 73-76

  Kim, Jae Joon ^a   Kim, Keunwoo ^a   Chuang, Ching Te ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; STATIC RANDOM ACCESS STORAGE;

DEVICE SIZING; GATE CONTROL; READ STABILITY; STABILITY IMPROVEMENT;

MOSFET DEVICES;

EID: 84943197732     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2006.307641     Document Type: Conference Paper

References (7)

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2. N. Azizi, F. Najm, and A. Moshovos, "Low Leakage Asymmetic-Cell SRAM," IEEE Trans. VLSI, vol. 11, no. 4, pp.701-711, Aug. 2003.
3. A. Pelella, A. Tuminaro, R. Fresse, and Y. Chan, "A 8Kb Domino Read SRAM with Hit Logic and Parity Checker,", ESSCIRC, pp. 12-16, Sep. 2005.
4. E. Seevinck. R. List and J. Lohstroh, "Staic-Noise Margin Analsys of MOS SRAM Cells," IEEE JSSC, vol. SC-22, pp. 748-754, Oct. 1987.
5. L. Matthew et. al, "CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)," IEEE SOI Conf. pp. 187-189, Oct. 2004.
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7. J-J. Kim, K. Kim, and C-T Chuang, "Back-Gate Controlled READ SRAM with improved Stability," IEEE SOI Conf. pp. 211-212, Oct. 2005.