A 8Kb Domino Read SRAM with Hit Logic and Parity Checker

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 359-362

  Pelella, Antonio R ^a   Tuminaro, Arthur D ^a   Freese, Ryan T ^a   Chan, Yuen H ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-LINE SEGMENTS; BIT-LINE STRUCTURES; BIT-LINE VOLTAGE DIFFERENTIALS; ROBUST OPERATION;

AMPLIFIERS (ELECTRONIC); ARRAYS; CAPACITANCE; DATA STORAGE EQUIPMENT; ELECTRIC BATTERIES; ROBUSTNESS (CONTROL SYSTEMS); STATIC RANDOM ACCESS STORAGE;

CMOS INTEGRATED CIRCUITS;

EID: 33749181684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541634     Document Type: Conference Paper

References (1)

1. E. Leobandung et al., High Performance 65 nm SOI Technology with Dual Stress Liner and low capacitance SRAM cell, Symposium on VLSI Technology, June, 2005