Automatic derivation of timing constraints by failure analysis

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2404, Issue , 2002, Pages 195-208

  Yoneda, Tomohiro ^a   Kitai, Tomoya ^b   Myers, Chris ^c  

^a NATIONAL INSTITUTE OF INFORMATICS   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^c UNIVERSITY OF UTAH   (United States)

Author keywords

Failure analysis; Timed circuits; Timing constraints; Trace theoretic verification

Indexed keywords

COMPUTER AIDED ANALYSIS; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; FAILURE (MECHANICAL); FAILURE ANALYSIS; INTEGER PROGRAMMING;

AUTOMATIC DERIVATION; BENCHMARK CIRCUIT; DELAY PARAMETERS; FAILURE TRACES; INTEGER LINEAR PROGRAMMING; TIMED CIRCUITS; TIMING CONSTRAINTS; TRACE THEORETIC VERIFICATION;

TIMING CIRCUITS;

EID: 84937569315     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45657-0_15     Document Type: Conference Paper

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