Relative timing based verification of timed circuits and systems

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2002, Pages 115-124

  Kim, Hoshik ^a   Beerel, Peter A ^a   Stevens, Ken ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUITS AND SYSTEMS; CONSTRAINT SET; ERROR-PRONE PROCESS; MANUAL IDENTIFICATION; RELATIVE TIMING; SUFFICIENT SET; TIMED CIRCUITS; TIMED SYSTEMS; TIMING CONSTRAINTS;

TIMING CIRCUITS;

EID: 77957937695     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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