Power-Optimal Pipelining in Deep Submicron Technology

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2004-January, Issue January, 2004, Pages 218-223

  Heo, Seongmoo ^a   Asanović, Krste ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Pipelining; Power Scaling; Supply Voltage Reduction

Indexed keywords

CLOCKS; FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; PIPE LININGS; POWER ELECTRONICS;

CLOCK FREQUENCY; DEEP SUB-MICRON TECHNOLOGY; POWER-SCALING; PREDICTIVE PROCESS; SUPPLY VOLTAGE REDUCTION; SUPPLY VOLTAGES; SWITCHING POWER; THREE COMPONENT;

THRESHOLD VOLTAGE;

EID: 84932130044     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2004.240996     Document Type: Conference Paper

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