UnSync-CMP: Multicore CMP architecture for energy-efficient soft-error reliability

IEEE Transactions on Parallel and Distributed Systems

Volumn 25, Issue 1, 2014, Pages 254-263

  Jeyapaul, Reiley ^a   Hong, Fei ^a   Rhisheekesan, Abhishek ^a   Shrivastava, Aviral ^a   Lee, Kyoungwoo ^b  

^a ARIZONA STATE UNIVERSITY   (United States)

^b Yonsei University   (South Korea)

Author keywords

CMP; Multicore architecture; power efficiency; reliability; soft error

Indexed keywords

BENCHMARKING; COST REDUCTION; ENERGY EFFICIENCY; ERROR CORRECTION; ERRORS; HARDWARE; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; RADIATION HARDENING; REDUNDANCY; RELIABILITY; SOFTWARE ARCHITECTURE;

ARCHITECTURE FRAMEWORKS; CMP; CYCLE-ACCURATE SIMULATION; MULTICORE ARCHITECTURES; PERFORMANCE EFFICIENCY; PERFORMANCE RELIABILITY; POWER EFFICIENCY; SOFT ERROR;

COMPUTER ARCHITECTURE;

EID: 84930653090     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2013.14     Document Type: Article

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