F6: Power/performance optimization of many-core processor SoCs

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 508-509

  Kosonocky, Stephen ^a   Stojanovic, Vladimir ^b   Van Berkel, Kees ^c   Chao, Ming Yang ^d   Knoll, Tobias ^e   Friedrich, Joshua ^f  

^a ADVANCED MICRO DEVICES   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c ST Ericsson   (Netherlands)

^d MEDIATEK INC   (Taiwan)

^e RWTH AACHEN UNIVERSITY   (Germany)

^f IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN CHALLENGES; DESIGN HIERARCHY; HIGH-PERFORMANCE PLATFORMS; MANY-CORE; MOBILE PLATFORM; ON CHIP COMMUNICATION; PANEL DISCUSSIONS; PERFORMANCE MODELING; PHYSICAL DESIGN; POWER EFFICIENT; POWER OPTIMIZATION; REAL-TIME APPLICATION; SYSTEM LEVELS;

DESIGN; MODELS; OPTIMIZATION; SYSTEMS ANALYSIS;

MICROPROCESSOR CHIPS;

EID: 84860654165     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177118     Document Type: Conference Paper

References (0)