SpiNNaker - Programming model

IEEE Transactions on Computers

Volumn 64, Issue 6, 2015, Pages 1769-1782

  Brown, Andrew D ^b   Furber, Steve B ^a   Reeve, Jeffrey S ^b   Garside, Jim D ^a   Dugan, Kier J ^b   Plana, Luis A ^a   Temple, Steve ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

Interconnection architectures; Neurocomputers; Parallel processors; Real time distributed

Indexed keywords

MESSAGE PASSING; PRINTED CIRCUIT BOARDS; SCALABILITY;

COMMUNICATION INFRASTRUCTURE; INTERCONNECTION ARCHITECTURE; LAY-OUT; MULTI-CORE COMPUTING; NEUROCOMPUTERS; PARALLEL PROCESSOR; PROGRAMMING MODELS; REAL TIME;

PRINTED CIRCUITS;

EID: 84929346727     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2014.2329686     Document Type: Article

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