-
2
-
-
57349089224
-
HMTT: A platform independent full-system memory trace monitoring system
-
Bao, Y., Chen, M., Ruan, Y., Liu, L., Fan, J., Yuan, Q., Song, B., Xu, J.: HMTT: a platform independent full-system memory trace monitoring system. In: Proceedings of the International Conference on Measurement and Modeling of Computer Systems, pp. 229–240 (2008)
-
(2008)
Proceedings of the International Conference on Measurement and Modeling of Computer Systems
, pp. 229-240
-
-
Bao, Y.1
Chen, M.2
Ruan, Y.3
Liu, L.4
Fan, J.5
Yuan, Q.6
Song, B.7
Xu, J.8
-
3
-
-
78650839010
-
Understanding the impact of emerging nonvolatile memories on high-performance, IO-intensive computing
-
Caulfield, A.M., Coburn, J., Mollov, T., De, A., Akel, A., He, J., Jagatheesan, A., Gupta, R.K., Snavely, A., Swanson, S.: Understanding the impact of emerging nonvolatile memories on high-performance, IO-intensive computing. In: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1–11 (2010)
-
(2010)
Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis
, pp. 1-11
-
-
Caulfield, A.M.1
Coburn, J.2
Mollov, T.3
De, A.4
Akel, A.5
He, J.6
Jagatheesan, A.7
Gupta, R.K.8
Snavely, A.9
Swanson, S.10
-
4
-
-
84867752658
-
Workload diversity and dynamics in big data analytics: Implications to system designers
-
Chang, J., Lim, K.T., Byrne, J., Ramirez, L., Ranganathan, P.: Workload diversity and dynamics in big data analytics: implications to system designers. In: Proceedings of the 2nd Workshop on Architectures and Systems for Big Data, pp. 21–26 (2012)
-
(2012)
Proceedings of the 2Nd Workshop on Architectures and Systems for Big Data
, pp. 21-26
-
-
Chang, J.1
Lim, K.T.2
Byrne, J.3
Ramirez, L.4
Ranganathan, P.5
-
6
-
-
84856987530
-
Extended scalability and functionalities of MRAM based on thermally assisted writing
-
Dieny, B., Sousa, R., Bandiera, S., Castro Souza, M., Auffret, S., Rodmacq, B., Nozieres, J., Herault, J., Gapihan, E., Prejbeanu, I., et al.: Extended scalability and functionalities of MRAM based on thermally assisted writing. In: Proceedings of the International Electron Devices Meeting, pp. 1–3 (2011)
-
(2011)
Proceedings of the International Electron Devices Meeting
, pp. 1-3
-
-
Dieny, B.1
Sousa, R.2
Bandiera, S.3
Castro Souza, M.4
Auffret, S.5
Rodmacq, B.6
Nozieres, J.7
Herault, J.8
Gapihan, E.9
Prejbeanu, I.10
-
7
-
-
84921641742
-
Characterizing data analysis workloads in data centers
-
Jia, Z., Wang, L., Zhan, J., Zhang, L., Luo, C.: Characterizing data analysis workloads in data centers. CoRR 1307.8013 (2013)
-
(2013)
Corr
, vol.1307
, pp. 8013
-
-
Jia, Z.1
Wang, L.2
Zhan, J.3
Zhang, L.4
Luo, C.5
-
8
-
-
84860664697
-
An 8mb multi-layered cross-pointReRAM macro with 443MB/s write throughput
-
Kawahara, A., Azuma, R., Ikeda, Y., Kawai, K., Katoh, Y., Tanabe, K., Nakamura, T., Sumimoto, Y., Yamada, N., Nakai, N., Sakamoto, S., Hayakawa, Y., Tsuji, K., Yoneda, S., Himeno, A., Origasa, K., Shimakawa, K., Takagi, T., Mikawa, T., Aono, K.: An 8mb multi-layered cross-pointReRAM macro with 443MB/s write throughput. In: Proceedings International Solid-State Circuits Conference, pp. 432–434 (2012)
-
(2012)
Proceedings International Solid-State Circuits Conference
, pp. 432-434
-
-
Kawahara, A.1
Azuma, R.2
Ikeda, Y.3
Kawai, K.4
Katoh, Y.5
Tanabe, K.6
Nakamura, T.7
Sumimoto, Y.8
Yamada, N.9
Nakai, N.10
Sakamoto, S.11
Hayakawa, Y.12
Tsuji, K.13
Yoneda, S.14
Himeno, A.15
Origasa, K.16
Shimakawa, K.17
Takagi, T.18
Mikawa, T.19
Aono, K.20
more..
-
9
-
-
83455209963
-
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems
-
Lee, H.G., Baek, S., Nicopoulos, C., Kim, J.: An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems. In: Proceedings of the International Computer Design Conference, pp. 381–387 (2011)
-
(2011)
Proceedings of the International Computer Design Conference
, pp. 381-387
-
-
Lee, H.G.1
Baek, S.2
Nicopoulos, C.3
Kim, J.4
-
10
-
-
84866852432
-
Identifying opportunities for byte-addressable non-volatile memory in extreme-scale scientific applications
-
Li, D., Vetter, J.S., Marin, G., McCurdy, C., Cira, C., Liu, Z., Yu, W.: Identifying opportunities for byte-addressable non-volatile memory in extreme-scale scientific applications. In: Proceedings International Parallel and Distributed Processing Symposium, pp. 945–956 (2012)
-
(2012)
Proceedings International Parallel and Distributed Processing Symposium
, pp. 945-956
-
-
Li, D.1
Vetter, J.S.2
Marin, G.3
McCurdy, C.4
Cira, C.5
Liu, Z.6
Yu, W.7
-
11
-
-
83755219446
-
STT-RAM based energy-efficiency hybrid cache for CMPs
-
Li, J., Xue, C., Xu, Y.: STT-RAM based energy-efficiency hybrid cache for CMPs. In: Proceedings of the International Conference on VLSI and System-on-Chip, pp. 31–36 (2011)
-
(2011)
Proceedings of the International Conference on VLSI and System-On-Chip
, pp. 31-36
-
-
Li, J.1
Xue, C.2
Xu, Y.3
-
12
-
-
52749085695
-
Understanding and designing new server architectures for emerging warehouse-computing environments
-
Lim, K., Ranganathan, P., Chang, J., Patel, C., Mudge, T.N., Reinhardt, S.: Understanding and designing new server architectures for emerging warehouse-computing environments. In: Proceedings of Annual International Symposium on Computer Architecture, pp. 315–326 (2008)
-
(2008)
Proceedings of Annual International Symposium on Computer Architecture
, pp. 315-326
-
-
Lim, K.1
Ranganathan, P.2
Chang, J.3
Patel, C.4
Mudge, T.N.5
Reinhardt, S.6
-
13
-
-
84921641741
-
Memory system characterization of big data workloads
-
Martin Dimitrov, Karthik Kumar, P.L., Viswanathan, V.: Memory system characterization of big data workloads. In: The 1st Workshop on Benchmarks, Performance Optimization, and Emerging hardware of Big Data Systems and Applications (2013)
-
(2013)
The 1St Workshop on Benchmarks, Performance Optimization, and Emerging Hardware of Big Data Systems and Applications
-
-
Dimitrov, M.1
Karthik Kumar, P.L.2
Viswanathan, V.3
-
14
-
-
42149105894
-
Write strategies for 2 and 4-bit multi-level phase-change memory
-
Nirschl, T., Phipp, J.B., Happ, T.D., Burr, G.W., Rajendran, B., Lee, M.H., Schrott, A., Yang, M., Breitwisch, M., Chen, C.F., Joseph, E., Lamorey, M., Cheek, R., Chen, S.H., Zaidi, S., Raoux, S., Chen, Y.C., Zhu, Y., Bergmann, R., Lung, H.L., Lam, C.: Write strategies for 2 and 4-bit multi-level phase-change memory. In: Proceedings of the International Electron Devices Meeting, pp. 461–464 (2007)
-
(2007)
Proceedings of the International Electron Devices Meeting
, pp. 461-464
-
-
Nirschl, T.1
Phipp, J.B.2
Happ, T.D.3
Burr, G.W.4
Rajendran, B.5
Lee, M.H.6
Schrott, A.7
Yang, M.8
Breitwisch, M.9
Chen, C.F.10
Joseph, E.11
Lamorey, M.12
Cheek, R.13
Chen, S.H.14
Zaidi, S.15
Raoux, S.16
Chen, Y.C.17
Zhu, Y.18
Bergmann, R.19
Lung, H.L.20
Lam, C.21
more..
-
15
-
-
79959583242
-
Page placement in hybrid memory systems
-
Ramos, L.E., Gorbatov, E., Bianchini, R.: Page placement in hybrid memory systems. In: Proceedings of the International Conference on Supercomputing, pp. 85–95 (2011)
-
(2011)
Proceedings of the International Conference on Supercomputing
, pp. 85-95
-
-
Ramos, L.E.1
Gorbatov, E.2
Bianchini, R.3
-
16
-
-
79959550547
-
DRAMSim2: A cycle accurate memory system simulator
-
Rosenfeld, P., Cooper-Balis, E., Jacob, B.: DRAMSim2: a cycle accurate memory system simulator. Comput. Archit. Lett. 10, 16–19 (2011)
-
(2011)
Comput. Archit. Lett
, vol.10
, pp. 16-19
-
-
Rosenfeld, P.1
Cooper-Balis, E.2
Jacob, B.3
-
17
-
-
79955889816
-
Relaxing nonvolatility for fast and energy-efficient stt-ram caches
-
Smullen, C., Mohan, V., Nigam, A., Gurumurthi, S., Stan, M.: Relaxing nonvolatility for fast and energy-efficient stt-ram caches. In: Proceedings of the International Symposium on High Performance Computer Architecture, pp. 50–61 (2011)
-
(2011)
Proceedings of the International Symposium on High Performance Computer Architecture
, pp. 50-56
-
-
Smullen, C.1
Mohan, V.2
Nigam, A.3
Gurumurthi, S.4
Stan, M.5
-
18
-
-
84866885060
-
On the role of NVRAM in dataintensive architectures: An evaluation
-
Van Essen, B., Pearce, R., Ames, S., Gokhale, M.: On the role of NVRAM in dataintensive architectures: an evaluation. In: Proceedings of the International Parallel Distributed Processing Symposium, pp. 703–714 (2012)
-
(2012)
Proceedings of the International Parallel Distributed Processing Symposium
, pp. 703-714
-
-
Van Essen, B.1
Pearce, R.2
Ames, S.3
Gokhale, M.4
-
19
-
-
84904011597
-
Bigdatabench: A big data benchmark suite from internet services
-
Wang, L., Luo, C., He, Y., Zhan, J., Zhan, K., Li, X., Zhu, Y., Zhang, S., Yang, Q., Qiu, B., Jia, Z.: Bigdatabench: a big data benchmark suite from internet services. In: Proceedings of the International Symposium On High Performance Computer Architecture (2014)
-
(2014)
Proceedings of the International Symposium on High Performance Computer Architecture
-
-
Wang, L.1
Luo, C.2
He, Y.3
Zhan, J.4
Zhan, K.5
Li, X.6
Zhu, Y.7
Zhang, S.8
Yang, Q.9
Qiu, B.10
Jia, Z.11
-
20
-
-
0029179077
-
The SPLASH-2 programs: Characterization and methodological considerations
-
Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 programs: characterization and methodological considerations. In: Proceedings of the International Symposium on Computer Architecture, pp. 24–36 (1995)
-
(1995)
Proceedings of the International Symposium on Computer Architecture
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
-
21
-
-
81355136046
-
Emerging non-volatile memories: Opportunities and challenges
-
Xue, C.J., Zhang, Y., Chen, Y., Sun, G., Yang, J.J., Li, H.: Emerging non-volatile memories: opportunities and challenges. In: Proc. International Conference on Hardware/Software Codesign and System Synthesis, pp. 325–334 (2011)
-
(2011)
Proc. International Conference on Hardware/Software Codesign and System Synthesis
, pp. 325-334
-
-
Xue, C.J.1
Zhang, Y.2
Chen, Y.3
Sun, G.4
Yang, J.J.5
Li, H.6
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