An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2011, Pages 381-387

  Lee, Hyung Gyu ^a   Baek, Seungcheol ^a   Nicopoulos, Chrysostomos ^b   Kim, Jongman ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF CYPRUS   (Cyprus)

Author keywords

[No Author keywords available]

Indexed keywords

ACHILLES' HEEL; CACHE ARCHITECTURE; DRAM TECHNOLOGY; ENERGY DELAY PRODUCT; HYBRID CONFIGURATIONS; HYBRID STRUCTURE; LOW-POWER CONSUMPTION; MAIN MEMORY; MEMORY TECHNOLOGY; MICROPROCESSOR ARCHITECTURES; NANOSCALE REGIME; NOVEL ARCHITECTURE; PHASE CHANGES; POWER EFFICIENCY; SUB-SYSTEMS;

DYNAMIC RANDOM ACCESS STORAGE; ENERGY UTILIZATION; NANOTECHNOLOGY; PHASE CHANGE MEMORY;

MEMORY ARCHITECTURE;

EID: 83455209963     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2011.6081427     Document Type: Conference Paper

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