Neighbor-cell assisted error correction for MLC NAND flash memories

SIGMETRICS 2014 - Proceedings of the 2014 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems

Volumn , Issue , 2014, Pages 491-504

  Cai, Yu ^a   Yalcin, Gulay ^b   Mutlu, Onur ^a   Haratsch, Erich F ^d   Unsal, Osman ^b   Cristal, Adrian ^b,c   Mai, Ken ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

^c ARTIFICIAL INTELLIGENCE RESEARCH INSTITUTE IIIA CSIC   (Spain)

^d LSI Corporation   (Spain)

Author keywords

ECC; Error Correction; Fault Tolerance; NAND flash memory; Program Interference; Threshold Voltage Distribution

Indexed keywords

CELLS; CYTOLOGY; ERROR CORRECTION; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; MEMORY ARCHITECTURE; NAND CIRCUITS; THRESHOLD VOLTAGE; VOLTAGE DISTRIBUTION MEASUREMENT;

CONDITIONAL DISTRIBUTION; CONVENTIONAL APPROACH; CONVENTIONAL TECHNIQUES; ERROR CORRECTION CODES; EXPERIMENTAL CHARACTERIZATION; NAND FLASH MEMORY; SOPHISTICATED MECHANISM; THRESHOLD VOLTAGE DISTRIBUTION;

FLASH MEMORY;

EID: 84904303751     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2591971.2591994     Document Type: Conference Paper

References (23)

1. Y. Cai et al., "Error Patterns in MLC NAND Flash Memory: Measurement, Characterization and Analysis", DATE 2012.
2. N. Mielke et al., "Bit Error Rate in NAND Flash Memories", IRPS 2008.
3. Y. Cai et al., "Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation", ICCD 2013.
4. Y. Cai et al. "Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling", DATE 2013.
5. K. Park et al., "A Zeroing Cell-to-cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories", JSSC 2008.
6. R. Liu et al., "Optimizing NAND Flash-Based SSDs via Retention Relaxation", FAST 2012.
7. Y. Cai et al. "Flash Correct-and-Refresh: Retention-Aware Error Management for Increased Flash Memory Lifetime", ICCD 2012.
8. Y. Cai et al., "Error Analysis and Retention-Aware Error Management for NAND flash memory," Intel Technology Journal 2013.
9. H. Shim et al., "Highly Reliable 26nm 64Gb MLC E2NAND Flash Memory with MSP Controller", VLSIT, 2011.
10. T. Kim et al., "Cell-to-cell Interference Compensation Schemes Using Reduced Symbol Pattern of Interfering Cells for MLC NAND Flash Memory", IEEE Transactions on Magnetics 2013.
11. G. Dong et al., "Using Data Postcompensation and Predistortion to Tolerate Cell-to-cell Interference in MLC NAND Flash Memory", IEEE Transactions on Circuits and Systems I, 2010.
12. S. Lin et al., "Error Control Coding (2nd Edition)", Prentice Hall 2004.
13. Y. Cai et al. "FPGA-Based Solid-State Drive Prototyping Platform", FCCM 2011.
14. J. Cha et al., "Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory Devices", ETRI Journal, 2013.
15. C. Kim et al., "A 21 nm High Performance 64 Gb MLC NAND Flash Memory with 400 MB/s Asynchronous Toggle DDR Interface", JSSC 2012.
16. D. Lee et al., "Estimation of NAND Flash Memory Threshold Voltage Distribution for Optimum Soft-Decision Error Correction", IEEE Transactions on Signal Processing 2013.
17. S. Yasarapu, "Architectural Requirements for MLC based SSDs", FMS 2011.
18. J. Bucy et al., "The DiskSim Simulation Environment Version 4.0 Reference Manual", Technical Report 2008.
19. N. Agrawal et al., "Design Tradeoffs for SSD Performance", USENIX 2008.
20. Open Source at HP Labs, http://tesla.hpl.hp.com/opensource
21. J. Katcher, "Postmark: a New File System Benchmark", Technical Report, 1997.
22. SNIA: IOTTA Repository, http://iotta.snia.org/tracetypes/3.
23. UMass Trace: http://traces.cs.umass.edu/index.php/Storage/Storage