A 21 nm high performance 64 Gb MLC NAND flash memory with 400 MB/s asynchronous toggle DDR interface

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 4, 2012, Pages 981-989

  Kim, Chulbum ^a   Ryu, Jinho ^a   Lee, Taesung ^a   Kim, Hyunggon ^a   Lim, Jaewoo ^a   Jeong, Jaeyong ^a   Seo, Seonghwan ^a   Jeon, Hongsoo ^a   Kim, Bokeun ^a   Lee, Inyoul ^a   Lee, Dooseop ^a   Kwak, Pansuk ^a   Cho, Seongsoon ^a   Yim, Yongsik ^a   Cho, Changhyun ^a   Jeong, Woopyo ^a   Park, Kwangil ^a   Han, Jin Man ^a   Song, Duheon ^a   Kyung, Kyehyun ^a   Lim, Young Ho ^a   Jun, Young Hyun ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

Asynchronous double data rate (DDR) interface; NAND flash memory; pseudo differential sensing

Indexed keywords

BIT LINES; DOUBLE DATA RATE; NAND FLASH; NAND FLASH MEMORY; ON CHIPS; PAGE SIZES; PRE-CHARGE; PROCESS TECHNOLOGIES; PSEUDO DIFFERENTIAL; SOFT DATA;

VLSI CIRCUITS;

NAND CIRCUITS;

EID: 84862797616     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2185341     Document Type: Conference Paper

References (7)

1. C. Dirik and B. Jacob, "The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device, architecture, and system organization," presented at the ISCA'09, Austin, TX, 2009.
2. D. Nobunaga et al., "A 50 nm 8 Gb NAND flash memory with 100 MB/s program throughput and 200 MB/s DDR interface," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 426-427.
3. H. Kim et al., "A 159 mm 32 nm 32 Gb MLC NAND-flash memory with 200 MB/s asynchronous DDR interface," in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 442-442.
4. G. Esch et al., "Near-linear CMOS I/O driver with less sensitive to process, voltage, and temperature variations," IEEE Trans. VLSI Syst., vol. 12, no. 11, pp. 1253-1257, Nov. 2004.
5. R. A. Cernea, "Highly compact non-volatile memory and method thereof ," U.S. patent 6,983,428, Jan. 3, 2006.
6. S. Y. Yoon, "Nonvolatilememory device and data randomizingmethod thereof," U.S. patent US2010/0259983, Oct. 14, 2010.
7. Y. Li et al., "A 16 Gb 3 b/cell NAND flash memory in 56 nm with 8 MB/s write rate," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 506-507.