A low-power, high-performance approximate multiplier with configurable partial error recovery

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2014, Pages

  Liu, Cong ^a   Han, Jie ^a   Lombardi, Fabrizio ^b  

^a UNIVERSITY OF ALBERTA   (Canada)

^b Northeastern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ENERGY EFFICIENCY;

ARITHMETIC CIRCUIT; DIGITAL SIGNAL PROCESSING (DSP); LOWER-POWER CONSUMPTION; MEAN ERROR DISTANCES; MOST SIGNIFICANT BIT; NEAREST NEIGHBORS; PROCESSING ACCURACIES; WALLACE MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 84903850362     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/DATE2014.108     Document Type: Conference Paper

References (10)

1. J. Han and M. Orshansky, "Approximate Computing: An Emerging Paradigm For Energy-Efficient Design," in IEEE ETS, 2013.
2. J. Huang, J. Lach, and G. Robins, "A methodology for energy-quality tradeoff using imprecise hardware," in DAC 2012, pp. 504-509.
3. J. Miao, K. He, A. Gerstlauer, and M. Orshansky, "Modeling and synthesis of quality-energy optimal approximate adders," in ICCAD 2012, pp. 728-735.
4. J. Liang, J. Han, and F. Lombardi, "New metrics for the reliability of approximate and probabilistic adders," IEEE Transactions on Computers, vol. 62, no. 9, pp. 1760-1771, 2013.
5. S.-L. Lu, "Speeding up processing with approximation circuits," Computer, vol. 37, no. 3, pp. 67-73, 2004.
6. P. Kulkarni, P. Gupta, and M. Ercegovac, "Trading accuracy for power with an underdesigned multiplier architecture," in 24th IEEE Intl. Conf. on VLSI Design, 2011, pp. 346-351.
7. K. Y. Kyaw, W. L. Goh, and K. S. Yeo, "Low-power high-speed multiplier for error-tolerant application," in IEEE Intl. Conf. Electron Devices and Solid-State Circuits (EDSSC), 2010, pp. 1-4.
8. B. Parhami, Computer arithmetic. Oxford university press, 2000.
9. N. H. Weste and H. David, CMOS VLSI Design-A Circuit and Systems Perspective, 3rd ed. Pearson Addison Wesley, 2005.
10. K. Bickerstaff, E. Swartzlander, and M. Schulte, "Analysis of column compression multipliers," in 15th IEEE Symp. on Computer Arithmetic, 2001, pp. 33-39.