High density 3D Silicon Interposer technology development and electrical characterization for high end applications

2012 4th Electronic System-Integration Technology Conference, ESTC 2012

Volumn , Issue , 2012, Pages

  Charbonnier, Jean ^a   Assous, Myriam ^a   Bally, Jean Philippe ^a   Miyairi, Ken ^b   Sunohara, Masahiro ^b   Cuchet, Robert ^a   Feldis, Helene ^a   Bouzaida, Nicole ^a   Bernard Henriques, Nathalie ^a   Hida, Rachid ^a   Mourier, Thierry ^a   Simon, Gilles ^a   Higashi, Mitsutoshi ^b  

^a CEA GRENOBLE   (France)

^b SHINKO ELECTRIC INDUSTRIES CO LTD   (Japan)

Author keywords

3D integration; Assembly; DC test; Silicon interposer; TSV

Indexed keywords

ASSEMBLY; CHIP SCALE PACKAGES; ELECTRONICS ENGINEERING; INTEGRATION; MOUNTINGS; SUBSTRATES;

3-D INTEGRATION; ELECTRICAL CHARACTERIZATION; ELECTRICAL PERFORMANCE; INTEGRATION CAPACITY; SILICON INTERPOSERS; TECHNOLOGICAL LEVEL; TECHNOLOGY DEVELOPMENT; TSV;

SILICON;

EID: 84902449562     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2012.6542156     Document Type: Conference Paper

References (12)

1. X. Zhang, et al, "Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21×21mm) Fine-Pitch Cu/low-k FCBGA Package", Proceedings of the 2009 Electric Components and Technology Conference (ECTC), San Diego, Calfornia, May 26-29, pp. 305-312, 2009.
2. C. S. Selvanayagam, et al, "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps", IEEE Transaction on Advanced Packaging, Vol. 32, No. 4, pp 720-728, November, 2009.
3. M. Sunohara, et al, "Silicon Interposer with TSVs (Through Silicon Vias) and Fine Multilayer Wiring", Proceedings of the 2008 Electric Components and Technology Conference (ECTC), Lake Buena Vista, Florida, May 27-30, pp. 847-852, 2008.
4. V. S. Rao, et al, "TSV Interposer Fabrication for 3D IC Packaging", Proceedings of the 2009 Electronics Packaging Technology Conference (EPTC), Singapore, December 9-11, pp. 431-437, 2009.
5. D. Malta, et al, "Fabrication of TSV-Based Silicon Interposers", 2010 IEEE International 3D Systems Integration Conference (3DIC), Munich, Germany, November 16-18, pp. 1-6, 2010.
6. M. Sunohara, et al, "Studies on Electrical Performance and Thermal Stress of a Silicon Interposer with TSVs", Proceedings of the 2010 Electric Components and Technology Conference (ECTC), Las Vegas, Nevada, June 1-4, pp. 1088-1093, 2010.
7. W.C. Chiou, et al, "An ultra-thin interposer utilizing 3D TSV technology", Proceeding of Symposium on VLSI Technology 2012, Honolulu, Hawaii, June 12-15, pp. 107-108, 2012.
8. I. De Wolf, et al, "Cu pumping in TSVs: Effect of pre-CMP thermal budget", Microelectronics Reliability, Vol 51, Issue 9-11, pp. 1856-1859, SEP-NOV 2011.
9. J. Charbonnier, et al," Integration of a Temporary Carrier in a TSV Process Flow", Proceedings of the 2009 Electric Components and Technology Conference (ECTC), San Diego, California, May 26-29, pp. 865-871, 2009.
10. J. Charbonnier, et al, "Development and characterization of a 3D technology including TSV and Cu pillars for high frequency applications", Proceedings of the 2010 Electric Components and Technology Conference (ECTC), Las Vegas, Nevada, June 1-4, pp. 1077-1082, 2010.
11. M. Assous, et al, «Porous dielectric dual damascene patterning issues for 65 nm node: can architecture bring a solution?», Proceedings of 2003 International Interconnect Technology Conference (IITC), Burlingame, California, June 02-04, 2003 pp. 97-99, 2003
12. International Technology Roadmap for Semiconductors 2005 Edition, Interconnect, p8.