TSV interposer fabrication for 3D IC packaging

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 431-437

  Rao, Vempati Srinivasa ^a   Wee, Ho Soon ^a   Sheng Vincent, Lee Wen ^a   Yu, Li Hong ^a   Ebin, Liao ^a   Nagarajan, Ranganathan ^a   Chong, Chai Tai ^a   Zhang, Xiaowu ^a   Damaruganath, Pinjala ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ADHESIVE BONDING; ADHESIVE MATERIALS; BACKGRINDING; BACKSIDE METALLIZATION; CHEMICAL-MECHANICAL POLISHING PROCESS; CLEANING CHEMICALS; DRIE PROCESS; FABRICATION PROCESS; HIGH TEMPERATURE; HIGH TEMPERATURE PROCESS; IC PACKAGING; LOW TEMPERATURES; METALLIZATION PROCESS; RE-DISTRIBUTION; TEST CHIPS; THERMAL OXIDES; THIN WAFERS; THROUGH-SILICON-VIA;

ASPECT RATIO; CHEMICAL CLEANING; CHEMICAL MECHANICAL POLISHING; CHEMICAL POLISHING; ELECTRONICS PACKAGING; FABRICATION; METALLIZING; NANOTECHNOLOGY; PACKAGING; PASSIVATION; SILICON WAFERS; THREE DIMENSIONAL;

WAFER BONDING;

EID: 77950947608     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2009.5416509     Document Type: Conference Paper

References (9)

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