19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 332-333

  Chang, Meng Fan ^a   Wu, Jui Jen ^a   Chien, Tun Fei ^a   Liu, Yen Chen ^a   Yang, Ting Chin ^a   Shen, Wen Chao ^a   King, Ya Chin ^a   Lin, Chorng Jung ^a   Lin, Ku Feng ^b   Chih, Yu Der ^b   Natarajan, Sreedhar ^b   Chang, Jonathan ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CELL RESISTANCE; EMBEDDED APPLICATION; ENERGY HARVESTER; HIGH CAPACITY; NON-VOLATILE MEMORY; RESISTIVE RAMS (RERAM); SENSE AMPLIFIER; SENSING MARGIN;

RANDOM ACCESS STORAGE;

EID: 84898075711     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757457     Document Type: Conference Paper

References (8)

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3. M.-F. Chang, et al., "A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time," ISSCC, pp. 434-435, 2012.
4. C. J. Chevallier et al., "A 0.13μm 64Mb Multi-Layered Conductive Metal-Oxide Memory," ISSCC, pp. 260-261, 2010.
5. A. Kawahara, et al. "An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput," ISSCC, pp. 432-433, 2012.
6. 2 2-layer 32Gb ReRAM memory device in 24nm technology," ISSCC, pp. 210-211, 2013.
7. W.-C. Shen, et al., "High-k metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process," IEDM, pp. 31.6.1-31.6.4, 2012.
8. X.-Y. Xue, et al., "A 0.13μm 8Mb logic based CuSiO resistive memory with self-adaptive yield enhancement and operation for power reduction," Symp. VLSI Tech., pp. 42-43, 2012.