DRuiD: Designing reconfigurable architectures with decision-making support

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2014, Pages 213-218

  Mariani, Giovanni ^a,b   Palermo, Gianluca ^b   Meeuws, Roel ^c   Sima, Vlad Mihai ^c   Silvano, Cristina ^b   Bertela, Koen ^a  

^a UNIVERSITY OF LUGANO   (Switzerland)

^b POLITECNICO DI MILANO   (Italy)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION DEVELOPMENT; APPLICATION REQUIREMENTS; COMPUTATIONAL ELEMENTS; DECISION MAKING SUPPORT; DEVELOPMENT PROCESS; HETEROGENEOUS COMPUTING; HETEROGENEOUS PLATFORMS; RECONFIGURABLE PLAT-FORMS;

COMPUTER AIDED DESIGN; EXPERT SYSTEMS; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84897903769     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2014.6742892     Document Type: Conference Paper

References (24)

1. E.s. Chung, P.a. Milder, J.c. Hoe, and Ken Mai. Single-chip heterogeneous computing: Does the future include custom logic, FPGAs, and GPGPUs? In Proceedings of MICRO, pages 225-236, 2010.
2. Y. Yankova, G. Kuzmanov, K. Bertels, G. Gaydadjiev, Yi Lu, and S. Vassiliadis. Dwarv: Delftworkbench automated reconfigurable vhdl generator. In Proceedings of FPL, pages 697-701, 2007.
3. Stephen Neuendorffer and Fernando Martinez-Vallina. Building zynq accelerators with vivado high level synthesis. In Proceedings of FPGA, pages 1-2, New York, NY, USA, 2013. ACM.
4. S. Lee, S.-j. Mn, and R. Eigenmann. OpenMP to gpgpu: a compiler framework for automatic translation and optimization. In Proceedings of PPoPP, pages 101-110, 2009.
5. Leo Breiman. Random forests. Mach. Learn., 45(1):5-32, October 2001.
6. G. Mariani, A. Brankovic, G. Palermo, J. Jovic, V. Zaccaria, and C. Silvano. A correlation-based design space exploration methodology for multi-processor systems-on-chip. In Proceedings of DAC, pages 120-125, 2010.
7. H. Cook and K. Skadron. Predictive design space exploration using genetically programmed response surfaces. In Proceedings of DAC, pages 960-965, 2008.
8. H.-Y. Liu and L. P. Carloni. On learning-based methods for design-space exploration with high-level synthesis. In DAC, pages 50-56, 2013.
9. A. Stulova, R. Leupers, and G. Ascheid. Throughput driven transformations of synchronous data flows for mapping to heterogeneous mpsocs. In Proceedings of SAMOS, pages 144-151, 2012.
10. G. Mariani, V. Sima, G. Palermo, V. Zaccaria, C. Silvano, and K. Bertels. Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures. In Proceedings of DATE, pages 1379-1384, march 2012.
11. A.d. Pimentel, C. Erbas, and S. Polstra. A systematic approach to exploring embedded system architectures at multiple abstraction levels. Computers, IEEE Transactions on, 55(2):99-112, 2006.
12. F. Ferrandi, P. L. Lanzi, C. Pilato, D. Sciuto, and A. Tumeo. Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems. 29(6):911-924, 2010.
13. K. Hoste and L. Eeckhout. Microarchitecture-independent workload characterization. Micro, IEEE, 27(3):63-72, may-june 2007.
14. Qi Guo, Tianshi Chen, Yunji Chen, Ling Li, and Weiwu Hu. Mcroarchitectural design space exploration made fast. Microprocessors and Microsystems, 37(1):41-51, 2013.
15. P. Giusto, G. Martin, and E. Harcourt. Reliable estimation of execution time of embedded software. In Proc. of DATE, pages 580-589, 2001.
16. G. R. Gupta, M. Gupta, and P. R. Panda. Rapid estimation of control delay from high-level specifications. In Proceedings of DAC, pages 455-458, 2006.
17. S. Khan, P. Xekalakis, J. Cavazos, and M. Cintra. Using predictive modeling for cross-program design space exploration in multicore systems. In Proceedings of PACT, pages 327-338, sept. 2007.
18. C. Zhang, A. Ravindran, K. Datta, A. Mukherjee, and B. Joshi. A machine learning approach to modeling power and performance of chip multiprocessors. In Proceedings of ICCD, pages 45-50, oct. 2011.
19. K.l.m. Bertels, S. A. Ostadzadeh, and R. J. Meeuws. Advanced profiling of applications for heterogeneous multi-core platforms. In Proceedings of ERSA, page 13, 2011.
20. Julian J. Faraway. Extending the Linear Model with R (Texts in Statistical Science). Chapman & Hall/CRC, 2005.
21. XILINX. ml510 documentation, 2008. http://www.xilinx.com/support/ documentation/ml510.htm.
22. Jason E. Fritts, Frederick W. Steiling, Joseph A. Tucek, and Wayne Wolf. Mediabench ii video: Expediting the next generation of video systems research. Microprocess. Microsyst., 33(4):301-318, June 2009.
23. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: a free, commercially representative embedded benchmark suite. In Proceedings of WWC, pages 3-14, 2001.
24. A. A. C. Experts. Cosy: Compiler system.