A machine learning approach to modeling power and performance of chip multiprocessors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2011, Pages 45-50

  Zhang, Changshu ^a   Ravindran, Arun ^a   Datta, Kushal ^a   Mukherjee, Arindam ^a   Joshi, Bharat ^a  

^a Department of Engineering Technology and Construction Management   (United States)

Author keywords

architecture; chip multiprocessor; CPI; machine learning; modeling; power

Indexed keywords

CHIP MULTIPROCESSOR; CPI; CYCLE ACCURATE; DESIGN PARAMETERS; DESIGN SPACES; EXHAUSTIVE SIMULATION; KERNEL CANONICAL CORRELATION ANALYSIS; LONG SIMULATION TIME; MACHINE-LEARNING; MEDIAN ERRORS; MICRO ARCHITECTURES; MODELING POWER; MULTITHREADED; PACKET PROCESSING; PERFORMANCE METRICS; POWER; PROCESSOR POWER; TRAINING SAMPLE;

ARCHITECTURE; COMPUTER SIMULATION; DESIGN; LEARNING ALGORITHMS; LEARNING SYSTEMS; MICROPROCESSOR CHIPS; MODELS; MULTIPROCESSING SYSTEMS; MULTITASKING; SYSTEMS ANALYSIS;

ELECTRIC LOSSES;

EID: 83455210694     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2011.6081374     Document Type: Conference Paper

References (19)

1. B.C. Lee, J. Collins, H. Wang, and D. Brooks, "CPR: Composable Performance Regression for Scalable Multiprocessor Models", 41st International symposium on Microarchitecture, 2008.
2. J.S. Taylor, N. Cristianini, "Kernel Methods for Pattern Analysis", Cambridge University Press, 2004.
3. X. Peng, M. Kasprowicz, M. Bergsneider, H. Xiao, "Improved Noninvasive Intracranial Pressure Assessment With Nonlinear Kernel Regression", IEEE Transactions on Information Technology in Biomedicine, Vol. 15, No. 4, July 2010, pp. 971-978.
4. J.J. Pan, J.T. Kwok, Q. Yang, and Y. Chen, "Multidimensional Vector Regression for Accurate and Low Cost Estimation in Pervasive Computing", IEEE Transaction on Knowledge and Data Engineering, Vol. 18, No.9, September 2006, pp. 1181-1193. (Pubitemid 44192186)
5. A. Ganapathi, H. Kuno, U. Daval, J. Wiener, A. Fox, M. Jordan, and D. Patterson, "Predicting Multiple Performance Metrics for Queries: Better Decisions Enabled by Machine Learning", International Conference on Data Engineering (ICDE), Shanghai, March 2009.
6. S. Akaho, "A kernel method for canonical correlation analysis", International Meeting of Psychometric Society (IMPS), 2001.
7. F.R. Bach, M.I. Jordan, "Kernel independent component analysis", Journal of Machine Learning Research, Vol. 3, 2002, pp. 1-48.
8. Sun Microsystems, "OpenSPARC T1 Micro-Archiecture Specification," ed, 2006.
9. A. Ganapathi, K. Datta, A. Fox, and D. Patterson, "A Case for Machine Learning to Optimize Multicore Performance", First USENIX Workshop on Hot Topics in Parallelism, 2009
10. M-metric, http://www.cs.princeton.edu/courses/archive/fall08/cos436/Duda/ PR-Mahal/M-metric.htm
11. Z. Wei and C. Yu, "New Generation of predictive technology model for sub-45nm design exploration", in 7th International Symposium on Quality Electronic Design(ISQED), 2006
12. Cacti, http://www.hpl.hp.com/research/cacti/
13. T. Wolf and M. Franklin, "CommBench-a telecommunications benchmark for network processors," IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2000.
14. F.A. Viana, "An algorithm for fast optimal Latin hypercube design of experiments", Intl. Journal for Numericxal Methods In Engineering, 2009.
15. E. Ipek, S.A. McKee, B. de Supinski, M. Schulz, and R. Caruana, "Efficiently exploring architectural design spaces via predictive modeling", Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.
16. S. Khan, P. Xekalakis, J. Cavazos, and M. Cintra, "Using predictive modeling for cross-program design space exploration in multicore systems", International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007.
17. th ACM Symposium on Architectural Support for Programming Languages and Operating Systems, 2002.
18. C. Dubach, T. M. Jones, and M. F.P. O'Boyle, "Exploring and Predicting the Architecture/Optimising Compiler Co-Design Space", in Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2008
19. th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-12), 2006