-
1
-
-
84876514971
-
USIMM: The utah SImulated memory module
-
UUCS-12-002
-
Niladrish Chatterjee, Rajeev Balasubramonian, Manjunath Shevgoor, Seth H. Pugsley, Aniruddha N. Udipi, Ali Shafiee, Kshitij Sudan, Manu Awasthi, and Zeshan Chishti. 2012. USIMM: The Utah SImulated Memory Module. Technical Report. University of Utah. UUCS-12-002.
-
(2012)
Technical Report. University of Utah
-
-
Chatterjee, N.1
Balasubramonian, R.2
Shevgoor, M.3
Pugsley, S.H.4
Udipi, A.N.5
Shafiee, A.6
Sudan, K.7
Awasthi, M.8
Chishti, Z.9
-
2
-
-
0032687058
-
A performance comparison of contemporary DRAM architectures
-
Vinodh Cuppu, Bruce Jacob, Brian Davis, and Trevor Mudge. 1999. A performance comparison of contemporary DRAM architectures. In ISCA-26.
-
(1999)
ISCA-26
-
-
Cuppu, V.1
Jacob, B.2
Davis, B.3
Mudge, T.4
-
3
-
-
47349120126
-
Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs
-
Mrinmoy Ghosh and Hsien-Hsin S. Lee. 2007. Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs. In MICRO-40.
-
(2007)
MICRO-40
-
-
Ghosh, M.1
Lee, H.-H.S.2
-
4
-
-
84872077062
-
Energy/performance design of memory hierarchies for processor-in-memory chips
-
Intelligent Memory Systems
-
Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas. 2001. Energy/Performance design of memory hierarchies for processor-in-memory chips. In Revised Papers from the 2nd International Workshop on Intelligent Memory Systems (IMS'00). Springer-Verlag, London, UK, 152-159. http://dl.acm.org/ citation.cfm?id=648002.743089 (Pubitemid 33332792)
-
(2001)
Lecture Notes in Computer Science
, Issue.2107
, pp. 152-159
-
-
Huang, M.1
Renau, J.2
Yoo, S.-M.3
Torrellas, J.4
-
5
-
-
76749145128
-
ESKIMO: Energy savings using semantic knowledge of inconsequential memory occupancy for DRAM subsystem
-
Ciji Isen and Lizy John. 2009. ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem. In MICRO-42.
-
(2009)
Micro-42
-
-
Isen, C.1
John, L.2
-
7
-
-
84897501409
-
-
JEDEC Committee JC-42.3 JEDEC Committee JC-42.3, Arlington, VA
-
JEDEC Committee JC-42.3 2012. JESD79-3F. JEDEC Committee JC-42.3, Arlington, VA.
-
(2012)
JESD79-3F
-
-
-
8
-
-
84897508009
-
-
JEDEC-DDR4. 2011. JS Choi DDR4 Mini Workshop. http://jedec.org/sites/ default/files/JS-Choi-DDR4-miniWorkshop.pdf.
-
(2011)
JS Choi DDR4 Mini Workshop
-
-
-
9
-
-
80052082854
-
Characterization of the variable retention time in dynamic random access memory
-
DOI
-
Heesang Kim, Byoungchan Oh, Younghwan Son, Kyungdo Kim, Seon-Yong Cha, Jae-Goan Jeong, Sung-Joo Hong, and Hyungcheol Shin. 2011. Characterization of the variable retention time in dynamic random access memory. IEEE Transactions on Electron Devices 58, 9, 2952-2958. DOI: http://dx.doi.org/10.1109/TED.2011. 2160066
-
(2011)
IEEE Transactions on Electron Devices
, vol.58
, Issue.9
, pp. 2952-2958
-
-
Kim, H.1
Oh, B.2
Son, Y.3
Kim, K.4
Cha, S.-Y.5
Jeong, J.-G.6
Hong, S.-J.7
Shin, H.8
-
11
-
-
84864834258
-
RAIDR: Retention-aware intelligent DRAM refresh
-
Jamie Liu, Ben Jaiyen, Richard Veras, and Onur Mutlu. 2012. RAIDR: Retention-Aware Intelligent DRAM Refresh. In ISCA. 1-12.
-
(2012)
ISCA
, pp. 1-12
-
-
Liu, J.1
Jaiyen, B.2
Veras, R.3
Mutlu, O.4
-
12
-
-
79953075520
-
Flikker: Saving DRAM refresh-power through critical data partitioning
-
Song Liu, Karthik Pattabiraman, Thomas Moscibroda, and Ben Zorn. 2011. Flikker: Saving DRAM refresh-power through critical data partitioning. In ASPLOS-XVI.
-
(2011)
ASPLOS-XVI
-
-
Liu, S.1
Pattabiraman, K.2
Moscibroda, T.3
Zorn, B.4
-
17
-
-
79951712962
-
Elastic refresh: Techniques to mitigate refresh penalties in high density memory
-
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, and Lizy K. John. 2010. Elastic refresh: Techniques to mitigate refresh penalties in high density memory. In MICRO-43.
-
(2010)
MICRO-43
-
-
Stuecheli, J.1
Kaseridis, D.2
Hunter, H.C.3
John, L.K.4
-
18
-
-
52649139073
-
A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies
-
IEEE Computer Society, Washington, DC DOI
-
Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, and Norman P. Jouppi. 2008a. A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies. In Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA'08). IEEE Computer Society, Washington, DC, 51-62. DOI: http://dx.doi.org/10.1109/ISCA.2008.16
-
(2008)
Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA'08)
, pp. 51-62
-
-
Thoziyoor, S.1
Ahn, J.H.2
Monchiero, M.3
Brockman, J.B.4
Jouppi, N.P.5
-
20
-
-
77954989143
-
Rethinking DRAM design and organization for energy-constrained multi-cores
-
Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, and Norman J. Jouppi. 2010. Rethinking DRAM design and organization for energy-constrained multi-cores. In ISCA-37.
-
(2010)
ISCA-37
-
-
Udipi, A.N.1
Muralimanohar, N.2
Chatterjee, N.3
Balasubramonian, R.4
Davis, A.5
Jouppi, N.J.6
-
21
-
-
33748930402
-
Retention-aware placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM
-
Ravi K. Venkatesan, Stephen Herr, and Eric Rotenberg. 2006. Retention-Aware Placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM. In HPCA-12.
-
(2006)
HPCA-12
-
-
Venkatesan, R.K.1
Herr, S.2
Rotenberg, E.3
-
22
-
-
77954995377
-
Reducing cache power with low-cost, multi-bit error-correcting codes
-
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, and Shih-lien Lu. 2010. Reducing cache power with low-cost, multi-bit error-correcting codes. In ISCA-37.
-
(2010)
ISCA-37
-
-
Wilkerson, C.1
Alameldeen, A.R.2
Chishti, Z.3
Wu, W.4
Somasekhar, D.5
Lu, S.-L.6
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