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Volumn 2107, Issue , 2001, Pages 152-159

Energy/performance design of memory hierarchies for processor-in-memory chips

Author keywords

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Indexed keywords


EID: 84872077062     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44570-6_11     Document Type: Conference Paper
Times cited : (2)

References (21)
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    • Brown, A.1
  • 2
    • 0030243819 scopus 로고    scopus 로고
    • Energy Dissipation In General Purpose Microprocessors
    • R. Gonzalez and M. Horowitz. Energy Dissipation In General Purpose Microprocessors. IEEE Journal on Solid-State Circuits, 31(4):1277–1284, September 1996.
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    • Gonzalez, R.1    Horowitz, M.2
  • 3
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    • Mapping Irregular Aplications to DIVA, a PIM-Based Data-Intensive Architecture
    • M. Hall et al. Mapping Irregular Aplications to DIVA, a PIM-Based Data-Intensive Architecture. In Supercomputing, November 1999.
    • (1999) Supercomputing
    • Hall, M.1
  • 4
    • 84945896300 scopus 로고    scopus 로고
    • IBM Microelectronics. Blue Logic SA-27E ASIC, February 1999
    • IBM Microelectronics. Blue Logic SA-27E ASIC. http://www.chips.ibm.com/news/1999/sa27e, February 1999.
  • 11
    • 0030285348 scopus 로고    scopus 로고
    • A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor
    • J. Montanaro et al. A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. IEEE Journal of Solid State Circuits, 31(11):1703–1714, November 1996.
    • (1996) IEEE Journal of Solid State Circuits , vol.31 , Issue.11 , pp. 1703-1714
    • Montanaro, J.1
  • 14
    • 0031096193 scopus 로고    scopus 로고
    • A Case for Intelligent DRAM
    • D. Patterson et al. A Case for Intelligent DRAM. IEEE Micro, pages 33–44, 1997.
    • (1997) IEEE Micro , pp. 33-44
    • Patterson, D.1
  • 18
    • 0031236158 scopus 로고    scopus 로고
    • Baring It All to Software: Raw Machines
    • E. Waingold et al. Baring It All to Software: Raw Machines. IEEE Computer, pages 86–93, September 1997.
    • (1997) IEEE Computer , pp. 86-93
    • Waingold, E.1
  • 19
    • 0030149507 scopus 로고    scopus 로고
    • CACTI: An Enhanced Cache Access and Cycle Time Model
    • S. Wilton and N. Jouppi. CACTI: An Enhanced Cache Access and Cycle Time Model. IEEE Journal on Solid-State Circuits, 31(5):677–688, May 1996.
    • (1996) IEEE Journal on Solid-State Circuits , vol.31 , Issue.5 , pp. 677-688
    • Wilton, S.1    Jouppi, N.2
  • 20
    • 0028062340 scopus 로고
    • The Design of a 55SPECint92 RISC Processor under 2W
    • N. Yeung et al. The Design of a 55SPECint92 RISC Processor under 2W. ISSCC Digest of Technical Papers, pages 206–207, February 1994.
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    • Yeung, N.1
  • 21
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    • FlexRAM Architecture Design Parameters. Technical Report CSRD-1584
    • University of Illinois at Urbana-Champaign
    • S-M. Yoo, J. Renau, M. Huang, and J. Torrellas. FlexRAM Architecture Design Parameters. Technical Report CSRD-1584, Department of Computer Science, University of Illinois at Urbana-Champaign, October 2000. http://iacoma.cs.uiuc.edu/flexram/publications.html.
    • (2000) Department of Computer Science
    • Yoo, S.-M.1    Renau, J.2    Huang, M.3    Torrellas, J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.