A case for Refresh Pausing in DRAM memory systems

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2013, Pages 627-638

  Nair, Prashant ^a   Chou, Chia Chen ^a   Qureshi, Moinuddin K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA INTEGRITY; DRAM CELLS; DRAM DEVICES; DRAM MEMORY; INTELLIGENT SCHEDULING; PERFORMANCE IMPROVEMENTS; READ LATENCIES; READ OPERATION;

COMPUTER ARCHITECTURE; SUPERCOMPUTERS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84880319502     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2013.6522355     Document Type: Conference Paper

References (18)

1. JESD79-3F, JEDEC Committee JC-42.3 Std. DDR3, 2010.
2. (2011) Js choi ddr4 miniworkshop. [Online]. Available: http://jedec.org/sites/default/files/JS-Choi-DDR4-miniWorkshop.pdf
3. J. Stuecheli, D. Kaseridis, H. C.Hunter, and L. K. John, "Elastic refresh: Techniques to mitigate refresh penalties in high density memory," in MICRO-43, 2010.
4. H. Kim, B. Oh, Y. Son, K. Kim, S.-Y. Cha, J.-G. Jeong, S.-J. Hong, and H. Shin, "Characterization of the variable retention time in dynamic random access memory," Electron Devices, IEEE Transactions on, vol. 58, no. 9, pp. 2952-2958, sept. 2011.
5. TN-47-16 Designing for High-Density DDR2 Memory, Micron, 2009.
6. B. L. Jacob, S. W. Ng, and D. T. Wang, Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann, 2008.
7. MT41J512M4:8Gb QuadDie DDR3 SDRAM-Rev. A 03/11, Micron, 2010.
8. A. Udipi et al., "Rethinking dram design and organization for energyconstrained multi-cores," in ISCA-37, 2010.
9. N. Chatterjee, R. Balasubramonian, M. Shevgoor, S. Pugsley, A. Udipi, A. Shafiee, K. Sudan, M. Awasthi, and Z. Chishti, "USIMM: the Utah SImulatedMemoryModule," University of Utah, Tech. Rep., 2012, uUCS-12-002.
10. (2012) Memory scheduling championship (msc). [Online]. Available: http://www.cs.utah.edu/~rajeev/jwac12/
11. R. K. Venkatesan, S. Herr, and E. Rotenberg, "Retention-aware placement in dram (rapid):software methods for quasi-non-volatile dram," in HPCA-12, 2006.
12. J. Kim and M. Papaefthymiou, "Block-based multi-period refresh for energy efficient dynamic memory," in ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International, 2001, pp. 193-197.
13. J. Liu, B. Jaiyen, R. Veras, and O. Mutlu, "Raidr: Retention-aware intelligent dram refresh," in ISCA, 2012, pp. 1-12.
14. M. Ghosh and H.-H. S. Lee, "Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3d diestacked drams," in MICRO-40, 2007.
15. C. Isen and L. John, "Eskimo: Energy savings using semantic knowledge of inconsequential memory occupancy for dram subsystem," in MICRO-42, 2009.
16. S. Liu et al., "Flikker: saving dram refresh-power through critical data partitioning," in ASPLOS-XVI, 2011.
17. C. Wilkerson et al., "Reducing cache power with low-cost, multi-bit error-correcting codes," in ISCA-37, 2010.
18. V. Cuppu, B. Jacob, B. Davis, and T.Mudge, "A performance comparison of contemporary dram architectures," in ISCA-26, 1999.