-
1
-
-
0021468626
-
WISARD, a radical new step forward in image recognition
-
10.1108/eb007637
-
Aleksander I, Thomas W, Bowden P (1984) WISARD, a radical new step forward in image recognition. Sensor Rev 4(3): 120-124
-
(1984)
Sensor Rev
, vol.4
, Issue.3
, pp. 120-124
-
-
Aleksander, I.1
Thomas, W.2
Bowden, P.3
-
2
-
-
84896941767
-
-
Prentice-Hall Englewood Cliffs
-
Alspector J (1991). VLSI architecture for neural networks: concepts, applications, and implementations, vol 1. Prentice-Hall, Englewood Cliffs, pp 180-213
-
(1991)
VLSI Architecture for Neural Networks: Concepts, Applications, and Implementations, Vol 1
, pp. 180-213
-
-
Alspector, J.1
-
5
-
-
0036979631
-
Design of a pipelined hardware architecture for real-time neural network computations
-
Tulsa, Okla, USA
-
Ayala JL et al. (2002) Design of a pipelined hardware architecture for real-time neural network computations. In: Proceedings of the 45th midwest symposium on circuits and systems MWSCAS'02 Tulsa, Okla, USA, vol 1, pp 419-422
-
(2002)
Proceedings of the 45th Midwest Symposium on Circuits and Systems MWSCAS'02
, vol.1
, pp. 419-422
-
-
Ayala, J.L.1
-
7
-
-
0024177160
-
A simple VLSI architecture for Neurocomputing
-
First annual Meeting, Boston, Massachusetts
-
Bavan P, Lee MS, Trealeven P (1988) A simple VLSI architecture for Neurocomputing. In: Proceedings of the International Neural Network Society. First annual Meeting, Boston, Massachusetts, p 398
-
(1988)
Proceedings of the International Neural Network Society
, pp. 398
-
-
Bavan, P.1
Lee, M.S.2
Trealeven, P.3
-
11
-
-
0026901296
-
PLA design for single-clock CMOS
-
10.1109/4.148332
-
Blair GM (1992) PLA design for single-clock CMOS. IEEE J Solid State Circuit 27(8): 1211-1213
-
(1992)
IEEE J Solid State Circuit
, vol.27
, Issue.8
, pp. 1211-1213
-
-
Blair, G.M.1
-
12
-
-
0029733454
-
Analog electronic cochlea design using multilexing switched capacitor circuits
-
10.1109/72.478400
-
Bor JC, Wu CY (1996) Analog electronic cochlea design using multilexing switched capacitor circuits. IEEE Trans Neural Netw 7(1): 155-166
-
(1996)
IEEE Trans Neural Netw
, vol.7
, Issue.1
, pp. 155-166
-
-
Bor, J.C.1
Wu, C.Y.2
-
15
-
-
0027657404
-
Implementation and performance of an analog nonvolatile neural network
-
10.1007/BF01254862
-
Castro HA, Tam SM, Holler MA (1993) Implementation and performance of an analog nonvolatile neural network. Analog Integr Circuits Signal Process 4(2): 97-113
-
(1993)
Analog Integr Circuits Signal Process
, vol.4
, Issue.2
, pp. 97-113
-
-
Castro, H.A.1
Tam, S.M.2
Holler, M.A.3
-
16
-
-
0025664998
-
Software to support massively parallel computing on the MasPar MP-1
-
Christy P (1990) Software to support massively parallel computing on the MasPar MP-1. In: Proceedings of COMPCON, pp 29-33
-
(1990)
Proceedings of COMPCON
, pp. 29-33
-
-
Christy, P.1
-
18
-
-
0026838206
-
GANGLION: A fast field programmable gate array implementation of a connectionist classifier
-
10.1109/4.121550
-
Cox CE, Blanz WE (1992) GANGLION: a fast field programmable gate array implementation of a connectionist classifier. IEEE J Solid State Circuits 3: 288-299
-
(1992)
IEEE J Solid State Circuits
, vol.3
, pp. 288-299
-
-
Cox, C.E.1
Blanz, W.E.2
-
22
-
-
0036131609
-
The Cam-Brain machine: An FPGA based hardware tool which evolves a 1000 neuron net module in seconds and updates a 75 million neuron artificial brain for real time robot
-
10.1016/S0925-2312(01)00593-8 1015.68144
-
De Garis H, Korkin M (2002) The Cam-Brain machine: an FPGA based hardware tool which evolves a 1000 neuron net module in seconds and updates a 75 million neuron artificial brain for real time robot. Neurocomput J 42(1-4): 35-68
-
(2002)
Neurocomput J
, vol.42
, Issue.1-4
, pp. 35-68
-
-
De Garis, H.1
Korkin, M.2
-
24
-
-
0034174025
-
The density advantage of configurable computing
-
10.1109/2.839320
-
Dehon A (2000) The density advantage of configurable computing. IEEE Comput 33(5): 41-49
-
(2000)
IEEE Comput
, vol.33
, Issue.5
, pp. 41-49
-
-
Dehon, A.1
-
26
-
-
0004700537
-
The use of neural networks in high energy physics
-
10.1162/neco.1993.5.4.505
-
Denby B (1993) The use of neural networks in high energy physics. Neural Comput 5(4): 505-549
-
(1993)
Neural Comput
, vol.5
, Issue.4
, pp. 505-549
-
-
Denby, B.1
-
27
-
-
0026867778
-
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
-
10.1109/72.129409
-
DeYong MR, Findley RL, Fields C (1992) The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element. IEEE Trans Neural Netw 3(3): 363-374
-
(1992)
IEEE Trans Neural Netw
, vol.3
, Issue.3
, pp. 363-374
-
-
Deyong, M.R.1
Findley, R.L.2
Fields, C.3
-
29
-
-
0034136215
-
Neural NETWORKS in analog hardware-design and implementation issues
-
Draghici S (2000) Neural NETWORKS IN analog hardware-design and implementation issues. Int J Neural Syst 1: 19-42
-
(2000)
Int J Neural Syst
, vol.1
, pp. 19-42
-
-
Draghici, S.1
-
31
-
-
45149138380
-
Learning on VLSI: A general-purpose digital neurochip
-
Duranton M, Sirat JA (1990) Learning on VLSI: a general-purpose digital neurochip. Philips J Res 45(1): 1-17
-
(1990)
Philips J Res
, vol.45
, Issue.1
, pp. 1-17
-
-
Duranton, M.1
Sirat, J.A.2
-
32
-
-
84897009820
-
-
PC Magazine, January 15 (accessed November 2011)
-
Dvorak JC (1991) Best of 1990: BrainMaker Professional, Version 1.5, PC Magazine, January 15. Available in the internet at: http://www.calsci.com/ referenc.html (accessed November 2011)
-
(1991)
Best of 1990: BrainMaker Professional, Version 1.5
-
-
Dvorak, J.C.1
-
35
-
-
16244400370
-
FPGA density enhancement of a neural network through run-time reconfiguration
-
Department of Electrical and Computer engineering, Brigham Young University
-
Eldredge JG (1994) FPGA density enhancement of a neural network through run-time reconfiguration. Master thesis Department of Electrical and Computer engineering, Brigham Young University
-
(1994)
Master Thesis
-
-
Eldredge, J.G.1
-
37
-
-
12744272731
-
ACME: A field programmable gate array implementation of a self adapting and scalable connectionist network
-
University of California SANTA CRUZ
-
Ferrucci AT (1994) ACME: a field programmable gate array implementation of a self adapting and scalable connectionist network. Master Thesis University of California SANTA CRUZ
-
(1994)
Master Thesis
-
-
Ferrucci, A.T.1
-
38
-
-
0026116327
-
A programmable analog neural network processor
-
10.1109/72.80332
-
Fisher WA et al (1991) A programmable analog neural network processor. IEEE Trans Neural Netw 2: 222-229
-
(1991)
IEEE Trans Neural Netw
, vol.2
, pp. 222-229
-
-
Fisher, W.A.1
-
39
-
-
0015401565
-
Some computer organization and their effectiveness
-
10.1109/TC.1972.5009071 0241.68020
-
Flynn MJ (1972) Some computer organization and their effectiveness. IEEE Trans Comput 21: 948-960
-
(1972)
IEEE Trans Comput
, vol.21
, pp. 948-960
-
-
Flynn, M.J.1
-
41
-
-
1642321176
-
A digital CMOS fully connected neural network within circuit learning capability and automatic identification of spurious attractors
-
Gascuel JD et al (1991) A digital CMOS fully connected neural network within circuit learning capability and automatic identification of spurious attractors. IEEE Conference on Euro ASIC, pp 247-250
-
(1991)
IEEE Conference on Euro ASIC
, pp. 247-250
-
-
Gascuel, J.D.1
-
42
-
-
84886679153
-
Implementing barrel shifters using multipliers
-
(accessed on November 2011)
-
Gigliotti P (2004) Implementing barrel shifters using multipliers. Application Note: XAPP195 (v1.1). Available in the internet at: http://www.xilinx.com (accessed on November 2011)
-
(2004)
Application Note: XAPP195 (v1.1)
-
-
Gigliotti, P.1
-
47
-
-
0025532312
-
A VLSI architecture for high-performance, low cost, on-chip learning
-
Hammerstrom D (1990) A VLSI architecture for high-performance, low cost, on-chip learning. Int Joint Conf Neural Netw 2: 537-543
-
(1990)
Int Joint Conf Neural Netw
, vol.2
, pp. 537-543
-
-
Hammerstrom, D.1
-
49
-
-
85153971230
-
-
MIT Press Cambridge
-
Hasler P, Diorio C, Minch BA, Mead C (1995) Single transistor learning synapses. Advances in neural information processing systems 2. MIT Press, Cambridge, pp 817-824
-
(1995)
Single Transistor Learning Synapses. Advances in Neural Information Processing Systems 2
, pp. 817-824
-
-
Hasler, P.1
Diorio, C.2
Minch, B.A.3
Mead, C.4
-
50
-
-
0004199140
-
-
Addison-Wesley Publishing Company Reading
-
Hecht-Nielsen R (1990) Neurocomputing. Addison-Wesley Publishing Company, Reading
-
(1990)
Neurocomputing
-
-
Hecht-Nielsen, R.1
-
52
-
-
0022882379
-
Data parallel algorithms
-
10.1145/7902.7903
-
Hillis WD, Steel GLJ (1986) Data parallel algorithms. Commun ACM 29(12): 1170-1183
-
(1986)
Commun ACM
, vol.29
, Issue.12
, pp. 1170-1183
-
-
Hillis, W.D.1
Steel, G.L.J.2
-
53
-
-
0024909727
-
An electrically trainable artificial neural network (ETANN) with 1024 floating gate synapse
-
Holler M et al (1989) An electrically trainable artificial neural network (ETANN) with 1024 floating gate synapse. In: Proceedings of IACNN, pp 191-196
-
(1989)
Proceedings of IACNN
, pp. 191-196
-
-
Holler, M.1
-
54
-
-
0026626172
-
Backpropagation simulations using limited precision calculations
-
Holt JL, Baker TE (1991) Backpropagation simulations using limited precision calculations. Int Joint Conf Neural Netw 2: 121-126
-
(1991)
Int Joint Conf Neural Netw
, vol.2
, pp. 121-126
-
-
Holt, J.L.1
Baker, T.E.2
-
55
-
-
33646918836
-
AMT DAP: A processor array in a workstation environment
-
Hunt DJ (1989) AMT DAP: a processor array in a workstation environment. Comput Syst Sci Eng 4(2): 107-114
-
(1989)
Comput Syst Sci Eng
, vol.4
, Issue.2
, pp. 107-114
-
-
Hunt, D.J.1
-
58
-
-
0026712578
-
Weight perturbation: An optimal architecture learning technique for Analog VLSI feed forward and recurrent multilayer networks
-
10.1109/72.105429
-
Jabri MA, Flower B (1992) Weight perturbation: an optimal architecture learning technique for Analog VLSI feed forward and recurrent multilayer networks. IEEE Trans Neural Netw 3(1): 154-157
-
(1992)
IEEE Trans Neural Netw
, vol.3
, Issue.1
, pp. 154-157
-
-
Jabri, M.A.1
Flower, B.2
-
59
-
-
0026367422
-
Distributing back propagation networks over the Intel iPSC Hypercube
-
Jackson D, Hammerstrom D (1991) Distributing back propagation networks over the Intel iPSC Hypercube. IEEE Int Joint Conf Neural Netw 1: 569-574
-
(1991)
IEEE Int Joint Conf Neural Netw
, vol.1
, pp. 569-574
-
-
Jackson, D.1
Hammerstrom, D.2
-
60
-
-
0013222481
-
A SIMD/dataflow architecture for a neurocomputer for spike-processing neural networks (NESPINN)
-
Jahnke A, Roth U, Klar H (1996) A SIMD/dataflow architecture for a neurocomputer for spike-processing neural networks (NESPINN), MicroNeuro'96, pp 232-237
-
(1996)
MicroNeuro'96
, pp. 232-237
-
-
Jahnke, A.1
Roth, U.2
Klar, H.3
-
62
-
-
77955292736
-
Comparative study on analog and gital neural networks
-
Kakkar V (2009) Comparative study on analog and gital neural networks. Int J Comput Sci Netw Secur (IJCSNS) 9(7): 14-19
-
(2009)
Int J Comput Sci Netw Secur (IJCSNS)
, vol.9
, Issue.7
, pp. 14-19
-
-
Kakkar, V.1
-
63
-
-
0242443310
-
An analog VLSI chip emulating sustained and transient response channels of the vertebrate retina
-
10.1109/TNN.2003.816343
-
Kameda S, Yagi T (2003) An analog VLSI chip emulating sustained and transient response channels of the vertebrate retina. IEEE Trans Neural Netw 14(5): 1405-1412
-
(2003)
IEEE Trans Neural Netw
, vol.14
, Issue.5
, pp. 1405-1412
-
-
Kameda, S.1
Yagi, T.2
-
64
-
-
0027634811
-
POPART: Practical optical implementation of adaptative resonance theory 2
-
10.1109/72.238323
-
Kane J, Paquin M (1993) POPART: practical optical implementation of adaptative resonance theory 2. IEEE Trans Neural Netw 4: 695-702
-
(1993)
IEEE Trans Neural Netw
, vol.4
, pp. 695-702
-
-
Kane, J.1
Paquin, M.2
-
65
-
-
0040080572
-
A parallel neurocomputer architecture towards billion connection updates per second
-
Kato H et al (1990) A parallel neurocomputer architecture towards billion connection updates per second. Int Joint Conf Neural Netw 2: 47-50
-
(1990)
Int Joint Conf Neural Netw
, vol.2
, pp. 47-50
-
-
Kato, H.1
-
66
-
-
0023538231
-
The warp computer: Architecture, implementation and performance
-
Kung HT (1987) The warp computer: architecture, implementation and performance. IEEE Trans Comput 36(12): 1523-1528
-
(1987)
IEEE Trans Comput
, vol.36
, Issue.12
, pp. 1523-1528
-
-
Kung, H.T.1
-
69
-
-
0027592698
-
A CMOS analog adaptive BAM with on-chip learning and weight refreshing
-
10.1109/72.217187
-
Linares-Barranco B, Sanchez-Sinencio E, Rodriguez-Vazquez A, Huertas J. L (1993) A CMOS analog adaptive BAM with on-chip learning and weight refreshing. IEEE Trans Neural Netw 4(3): 445-455
-
(1993)
IEEE Trans Neural Netw
, vol.4
, Issue.3
, pp. 445-455
-
-
Linares-Barranco, B.1
Sanchez-Sinencio, E.2
Rodriguez-Vazquez, A.3
Huertas, J.L.4
-
72
-
-
0023331258
-
An Introduction to computing with neural nets
-
10.1109/MASSP.1987.1165576
-
Lippmann RP (1987) An Introduction to computing with neural nets. IEEE ASSP Mag 4(2): 4-22
-
(1987)
IEEE ASSP Mag
, vol.4
, Issue.2
, pp. 4-22
-
-
Lippmann, R.P.1
-
73
-
-
84896912482
-
Dynamically reconfigurable logic in undergraduate projects
-
Moore W, Luk W (eds) FPGAs England
-
Lysaght P (1991) Dynamically reconfigurable logic in undergraduate projects. In: Moore W, Luk W (eds) FPGAs. Abingdon EE&CS Books, England
-
(1991)
Abingdon EE&CS Books
-
-
Lysaght, P.1
-
76
-
-
51249194645
-
A logical calculus of ideas immanent in nervous activity
-
10.1007/BF02478259 0063.03860 10388
-
McCulloch W, Pitts V (1943) A logical calculus of ideas immanent in nervous activity. Bull Math Biophys 5: 115-133
-
(1943)
Bull Math Biophys
, vol.5
, pp. 115-133
-
-
McCulloch, W.1
Pitts, V.2
-
78
-
-
0026868201
-
The TINMANN VLSI chip
-
10.1109/72.129410 2367652
-
Melton M et al (1992) The TINMANN VLSI chip. IEEE Trans Neural Netw 3(3): 375-384
-
(1992)
IEEE Trans Neural Netw
, vol.3
, Issue.3
, pp. 375-384
-
-
Melton, M.1
-
79
-
-
42549092701
-
Fish inspection system using a parallel neural network chip and the image knowledge builder application
-
Menendez A, Paillet G (2008) Fish inspection system using a parallel neural network chip and the image knowledge builder application. Artif Intell Mag 29(1): 21-28
-
(2008)
Artif Intell Mag
, vol.29
, Issue.1
, pp. 21-28
-
-
Menendez, A.1
Paillet, G.2
-
80
-
-
80052655519
-
Evolvable block-based neural network design for applications in dynamic environments
-
doi: 10.1155/2010/251210
-
Merchant SG, Peterson GD (2010) Evolvable block-based neural network design for applications in dynamic environments. VLSI Design Hindawi Publishing Corporation. doi: 10.1155/2010/251210
-
(2010)
VLSI Design Hindawi Publishing Corporation
-
-
Merchant, S.G.1
Peterson, G.D.2
-
82
-
-
54249090769
-
On the arithmetic precision for implementing back-propagation networks on FPGA: A case study
-
A.R. Omondi J.C. Rajapakse (eds) Springer Berlin 10.1007/0-387-28487-7-2
-
Moussa M, Areibi S, Nichols K (2006) On the arithmetic precision for implementing back-propagation networks on FPGA: a case study. In: Omondi AR, Rajapakse JC (eds) FPGA implementations of neural networks. Springer, Berlin, pp 37-61
-
(2006)
FPGA Implementations of Neural Networks
, pp. 37-61
-
-
Moussa, M.1
Areibi, S.2
Nichols, K.3
-
84
-
-
51049121565
-
An IP core and GUI for implementing multilayer perceptron with a fuzzy activation function on configurable logic devices
-
Munoz AR et al (2008) An IP core and GUI for implementing multilayer perceptron with a fuzzy activation function on configurable logic devices. J Univers Comput Sci 14(10): 1678-1694
-
(2008)
J Univers Comput Sci
, vol.14
, Issue.10
, pp. 1678-1694
-
-
Munoz, A.R.1
-
85
-
-
3342936588
-
A novel computational and signaling method for VLSI neural networks
-
Murray AF, Smith AVW (1987) A novel computational and signaling method for VLSI neural networks. European solide state circuit conference, pp 19-22
-
(1987)
European Solide State Circuit Conference
, pp. 19-22
-
-
Murray, A.F.1
Avw, S.2
-
86
-
-
0023361987
-
Asynchronous VLSI neural networks using pulse stream arithmetic
-
10.1109/4.307
-
Murray AF, Smith AVW (1988) Asynchronous VLSI neural networks using pulse stream arithmetic. IEEE J Solid State Circuits 23(3): 688-697
-
(1988)
IEEE J Solid State Circuits
, vol.23
, Issue.3
, pp. 688-697
-
-
Murray, A.F.1
Smith, A.V.W.2
-
87
-
-
0026116469
-
Pulse stream VLSI networks mixing analog and digital techniques
-
10.1109/72.80329
-
Murray AF et al (1991) Pulse stream VLSI networks mixing analog and digital techniques. IEEE Trans Neural Netwo 2(2): 193-204
-
(1991)
IEEE Trans Neural Netwo
, vol.2
, Issue.2
, pp. 193-204
-
-
Murray, A.F.1
-
88
-
-
84896930616
-
NC3003-Digital Processor for Neural Networks
-
(accessed on November 2011)
-
NC3003-Digital Processor for Neural Networks (2011) Data sheet, Rel. 12/99 available in the internet at: http://www.digchip.com/datasheets/parts/ datasheet/327/NC3003-pdf.php (accessed on November 2011)
-
(2011)
Data Sheet, Rel. 12/99
-
-
-
90
-
-
51049084463
-
A reconfigurable computing architecture for implementing artificial neural networks on FPGA
-
University of Guelph
-
Nichols KR (2004) A reconfigurable computing architecture for implementing artificial neural networks on FPGA. Master Thesis, University of Guelph
-
(2004)
Master Thesis
-
-
Nichols, K.R.1
-
91
-
-
84889959687
-
Sparse distributed memory simulation on REMAP3
-
Luleå University of Technology, Sweden
-
o TULEA 1991:16, Luleå University of Technology, Sweden
-
(1991)
O TULEA
, vol.16
-
-
Nordstrom, T.1
-
95
-
-
0027879346
-
ANN accelerator by parallel processor based on DSP
-
Onuki J, Maenosono T et al (1993) ANN accelerator by parallel processor based on DSP. In: Proceedings of the IJCNN-93-Nagoya, pp 1913-1916
-
(1993)
Proceedings of the IJCNN-93-Nagoya
, pp. 1913-1916
-
-
Onuki, J.1
Al Et, M.T.2
-
96
-
-
0027883471
-
A mixed-mode architecture for implementation of analog neural networks with digital programmability
-
Nagoya, Japan
-
Passos Almeida A, Franca JE (1993) A mixed-mode architecture for implementation of analog neural networks with digital programmability. In: Proceedings of the International Joint Conference on Neural Networks (IJCNN'93), Nagoya, Japan, vol 1, pp 887-890
-
(1993)
Proceedings of the International Joint Conference on Neural Networks (IJCNN'93)
, vol.1
, pp. 887-890
-
-
Passos Almeida, A.1
Franca, J.E.2
-
97
-
-
33746917173
-
Design and FPGA implementation of an embedded real-time biologically plausible spiking neural network processor
-
Pearson MJ et al (2005) Design and FPGA implementation of an embedded real-time biologically plausible spiking neural network processor. International Conference on Field Programmable Logic and Applications, pp 582-585
-
(2005)
International Conference on Field Programmable Logic and Applications
, pp. 582-585
-
-
Pearson, M.J.1
-
98
-
-
0028732519
-
Implementation of a fully parallel Kohonen map: A mixed analog/digital approach
-
Peiris V, Hochet B, Declercq M (1994) Implementation of a fully parallel Kohonen map: a mixed analog/digital approach. IEEE Int Conf Neural Netw 4: 2064-2069
-
(1994)
IEEE Int Conf Neural Netw
, vol.4
, pp. 2064-2069
-
-
Peiris, V.1
Hochet, B.2
Declercq, M.3
-
99
-
-
18144423305
-
-
PhD thesis 2052, Logic System laboratory, Computer Science department, Swiss federal Institute of Technology- Lausanne
-
Peres-Uribe A (1999) Structure adaptable digital neural networks. PhD thesis 2052, Logic System laboratory, Computer Science department, Swiss federal Institute of Technology- Lausanne
-
(1999)
Structure Adaptable Digital Neural Networks
-
-
Peres-Uribe, A.1
-
100
-
-
0141811271
-
Implementation of artificial neural networks on a reconfigurable hardware accelerator
-
doi: 10.1109/EMPDP.2002.994279
-
Porrmann M (2002) Implementation of artificial neural networks on a reconfigurable hardware accelerator. 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, pp 243-250. doi: 10.1109/EMPDP.2002. 994279
-
(2002)
10th Euromicro Workshop on Parallel, Distributed and Network-based Processing
, pp. 243-250
-
-
Porrmann, M.1
-
103
-
-
6644220302
-
Systolic synthesis of neural networks
-
10.1007/978-94-009-0643-3-6
-
Ramacher U, Wesseling M (1990) Systolic synthesis of neural networks. Int Neural Netw Conf 2: 572-576
-
(1990)
Int Neural Netw Conf
, vol.2
, pp. 572-576
-
-
Ramacher, U.1
Wesseling, M.2
-
106
-
-
70349878787
-
Investigating the suitability of FPAAs for evolved hardware spiking neural networks
-
Rocke P, McGinley B, Maher J, Morgan F, Harkin J (2008) Investigating the suitability of FPAAs for evolved hardware spiking neural networks. In: ICES 2008, LNCS 5216, pp 118-129
-
(2008)
ICES 2008, LNCS
, vol.5216
, pp. 118-129
-
-
Rocke, P.1
McGinley, B.2
Maher, J.3
Morgan, F.4
Harkin, J.5
-
107
-
-
0025401319
-
Non linear switched capacitor neural networks for optimization problems
-
10.1109/31.52732
-
Rodriguez A, Dominguez CR, Rueda A, Huertas RL, Sanchez-sinenco E (1990) Non linear switched capacitor neural networks for optimization problems. IEEE Trans Circuits Syst 37(3): 384-398
-
(1990)
IEEE Trans Circuits Syst
, vol.37
, Issue.3
, pp. 384-398
-
-
Rodriguez, A.1
Dominguez, C.R.2
Rueda, A.3
Huertas, R.L.4
Sanchez-Sinenco, E.5
-
108
-
-
84896990457
-
A robot vision system using a silicon retina
-
10.1007/978-3-642-04025-2-23 10.1007/978-3-642-04025-2-23
-
Sanada A, Ishii K, Yagi T (2010) A robot vision system using a silicon retina. Brain Inspir Inf Technol 266: 135-139. doi: 10.1007/978-3-642-04025-2-23
-
(2010)
Brain Inspir Inf Technol
, vol.266
, pp. 135-139
-
-
Sanada, A.1
Ishii, K.2
Yagi, T.3
-
109
-
-
0027855197
-
Development of a highperformance, general purpose neuro-computer composed of 512 digital neurons
-
Nagoya, Japan
-
Sato Y et al (1993) Development of a highperformance, general purpose neuro-computer composed of 512 digital neurons. In: Proceedings of the International Joint Conference on Neural Networks (IJCNN '93), Nagoya, Japan, vol 2, pp 1967-1970
-
(1993)
Proceedings of the International Joint Conference on Neural Networks (IJCNN '93)
, vol.2
, pp. 1967-1970
-
-
Sato, Y.1
-
111
-
-
84957033912
-
Speeding up hardware evolution: A coprocessor for evolutionary algorithms
-
10.1007/3-540-36553-2-25
-
Schmitz T, Hohmann S, Meier K, Schemmel J, Schurmann F (2003) Speeding up hardware evolution: a coprocessor for evolutionary algorithms. Evolv Syst Biol Hardw Lect Notes Comput Sci 2606: 274-285
-
(2003)
Evolv Syst Biol Hardw Lect Notes Comput Sci
, vol.2606
, pp. 274-285
-
-
Schmitz, T.1
Hohmann, S.2
Meier, K.3
Schemmel, J.4
Schurmann, F.5
-
112
-
-
0026219157
-
CMOS mean field learning
-
10.1049/el:19911060
-
Schneider CR, Card HC (1991) CMOS mean field learning. Electron Lett 27(19): 1702-1704
-
(1991)
Electron Lett
, vol.27
, Issue.19
, pp. 1702-1704
-
-
Schneider, C.R.1
Card, H.C.2
-
113
-
-
84874561573
-
Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
-
Schrauwen B, Van Campenhout J (2006) Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic. In: Proceedings of ESANN, pp 623-628
-
(2006)
Proceedings of ESANN
, pp. 623-628
-
-
Schrauwen, B.1
Van Campenhout, J.2
-
114
-
-
0000383868
-
Parallel networks that learn to pronounce English text
-
Sejnowski TJ, Rosenberg CR (1987) Parallel networks that learn to pronounce English text. Complex Syst 1:145-168
-
(1987)
Complex Syst
, vol.1
, pp. 145-168
-
-
Sejnowski, T.J.1
Rosenberg, C.R.2
-
116
-
-
0026998980
-
Neuro chips with on-chip back-propagation and/or hebbian learning
-
10.1109/4.173117
-
Shima T et al (1992) Neuro chips with on-chip back-propagation and/or hebbian learning. IEEE J Solid State Circuts 27: 1868-1876
-
(1992)
IEEE J Solid State Circuts
, vol.27
, pp. 1868-1876
-
-
Shima, T.1
-
118
-
-
0033280020
-
Fast neural network implementation
-
Skrbek M (1999) Fast neural network implementation. Neural Netw World 9(5): 375-391
-
(1999)
Neural Netw World
, vol.9
, Issue.5
, pp. 375-391
-
-
Skrbek, M.1
-
121
-
-
0027810666
-
Backpropagation learning in analog T-model neural network hardware
-
Nagoya, Japan
-
Tang T, Ishizuka O, Matsumoto H (1993) Backpropagation learning in analog T-model neural network hardware. In: Proceedings of the International Joint Conference on Neural Networks (IJCNN '93), Nagoya, Japan, vol 1, pp 899-902
-
(1993)
Proceedings of the International Joint Conference on Neural Networks (IJCNN '93)
, vol.1
, pp. 899-902
-
-
Tang, T.1
Ishizuka, O.2
Matsumoto, H.3
-
122
-
-
70349966256
-
A reconfigurable SIMD computer for artificial neural networks
-
Department of Computer Engineering Chalmers, University of Technology, Goteborg, Sweden
-
Tavenik M, Linde A (1995) A reconfigurable SIMD computer for artificial neural networks. Licentiate thesis No 189L. Department of Computer Engineering Chalmers, University of Technology, Goteborg, Sweden
-
(1995)
Licentiate Thesis No 189L
-
-
Tavenik, M.1
Linde, A.2
-
126
-
-
0023389776
-
Switched-capacitor neural networks
-
10.1049/el:19870674
-
Tsividis Y, Anastassiou D (1987) Switched-capacitor neural networks. Electron Lett 23(18): 958-959
-
(1987)
Electron Lett
, vol.23
, Issue.18
, pp. 958-959
-
-
Tsividis, Y.1
Anastassiou, D.2
-
128
-
-
18144426404
-
An FPGA platform for on-line topology exploration of spiking neural networks
-
10.1016/j.micpro.2004.08.012
-
Upegui A, Pena-Reyes CA, Sanchez E (2005) An FPGA platform for on-line topology exploration of spiking neural networks. Microprocess Microsyst Elsevier 29: 211-223
-
(2005)
Microprocess Microsyst Elsevier
, vol.29
, pp. 211-223
-
-
Upegui, A.1
Pena-Reyes, C.A.2
Sanchez, E.3
-
130
-
-
0024903879
-
Neural network simulation on a massively parallel cellular array processor: AAP-2
-
Washington DC
-
Watanabe T et al (1989) Neural network simulation on a massively parallel cellular array processor: AAP-2. International Joint Conference on Neural Networks, Washington DC, vol 2, pp 155-161
-
(1989)
International Joint Conference on Neural Networks
, vol.2
, pp. 155-161
-
-
Watanabe, T.1
-
133
-
-
0011812668
-
Training algorithms for limited precision feed forward neural networks
-
Xie Y, Jabri MA (1991) Training algorithms for limited precision feed forward neural networks. Technical report SEPAL
-
(1991)
Technical Report SEPAL
-
-
Xie, Y.1
Ma, J.2
-
134
-
-
0024910802
-
A wafer scale integration neural network utilizing completely digital circuits
-
10.1109/IJCNN.1989.118701
-
Yasunaga M et al (1989) A wafer scale integration neural network utilizing completely digital circuits. Int Joint Conf Neural Netw 2: 213-217
-
(1989)
Int Joint Conf Neural Netw
, vol.2
, pp. 213-217
-
-
Yasunaga, M.1
-
135
-
-
84897017228
-
Recent developments of the snns neural network simulator
-
Zell A, Korb T, Sommer T, Bayer R (1990) Recent developments of the snns neural network simulator. In: Proceedings of the applications of neural networks conference, SPIE 1294, pp 534-544
-
(1990)
Proceedings of the Applications of Neural Networks Conference, SPIE
, vol.1294
, pp. 534-544
-
-
Zell, A.1
Korb, T.2
Sommer, T.3
Bayer, R.4
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