Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic

ESANN 2006 Proceedings - European Symposium on Artificial Neural Networks

Volumn , Issue , 2006, Pages 623-628

  Schrauwen, Benjamin ^a   Van Campenhout, Jan ^a  

^a GHENT UNIVERSITY   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NEURONS;

HARDWARE IMPLEMENTATIONS; IMPLEMENTATION ARCHITECTURE; INTEGRATE AND FIRES; PARALLEL HARDWARE; PARALLEL PROCESSING; SERIAL PROCESSING; SPIKING NEURAL NETWORKS; SPIKING NEURON;

NEURAL NETWORKS;

EID: 84874561573     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. W. Gerstner and W. M. Kistler. Spiking Neuron Models. Cambridge University Press, 2002.
2. H. Hellmich, M. Geike, P. Griep, P. Mahr, M. Rafanelli, and H. Klar. Emulation engine for spiking neurons and adaptive synaptic weights. In Proc. of IJCNN, pages 3261-3266, 2005.
3. D. Roggen, S. Hofmann, Y. Thoma, and D. Floreano. Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot. In NASA/DoD Conf. on Evolvable Hardware, pages 189-198, 2003.
4. A. Upegui, C. A. Peña Reyes, and E. Sanchez. An FPGA platform for on-line topology exploration of spiking neural networks. Microprocessors and Microsystems, 29:211-223, 2005.
5. D. Verstraeten, B. Schrauwen, D. Stroobandt, and J. Van Campenhout. Isolated word recognition with the liquid state machine: a case study. Information Processing Letters, 95(6):521-528, 2005.
6. J. Waldemark, M. Millberg, T. Lindblad, K. Waldemark, and V. Becanovic. Implementation of a pulse coupled neural network in FPGA. International Journal of Neural Systems, 10(3):171-177, 2000.