Design of a pipelined hardware architecture for real-time neural network computations

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages I419-I422

  Ayala, J L ^a   Lomena A G ^a   Lopez Vallejo M ^a   Fernandez A ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DATA ACQUISITION; LEARNING ALGORITHMS; SERVERS;

DATA QUANTIZATION EFFECTS;

NEURAL NETWORKS;

EID: 0036979631     PISSN: None     EISSN: None     Source Type: Journal    
DOI: 10.1109/MWSCAS.2002.1187247     Document Type: Article

References (12)

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