Proof engineering in the large: Formal verification of Pentium®4 floating-point divider

International Journal on Software Tools for Technology Transfer

Volumn 4, Issue 3, 2003, Pages 323-334

  Kaivola, Roope ^a   Kohatsu, Katherine ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Arithmetic; Formal verification; Microprocessor

Indexed keywords

FLOATING POINT DIVISIONS; FLOATING-POINT DIVIDER; FORMAL VERIFICATIONS; FULLY AUTOMATED; PENTIUM; PROOF ENGINEERING; SQUARE ROOT UNITS; VERIFICATION METHODOLOGY;

DIGITAL ARITHMETIC; MICROPROCESSOR CHIPS; MODEL CHECKING;

THEOREM PROVING;

EID: 84896693478     PISSN: 14332779     EISSN: 14332787     Source Type: Journal    
DOI: 10.1007/s10009-002-0081-6     Document Type: Article

References (24)

1. Aagaard, M.D., Jones, R.B., Seger, C.J.H.: Lifted-fl: a pragmatic implementation of combined model checking and theorem proving. In: Theorem Proving in Higher-Order Logics, Lecture Notes in Computer Science, vol. 1690. Springer, Berlin Heidelberg New York, 1999
2. Aagaard, M.D., Melham, T.F., O'Leary, J.W.: Xs are for trajectory evaluation, Booleans are for theorem proving. In: Correct Hardware Design and Verification Methods, Lecture Notes in Computer Science, vol. 1703. Springer, Berlin Heidelberg New York, 1999
3. Bhadra, J., Martin, A., Abraham, J., Abadir, M.: Using abstract specifications to verify PowerPC custom memories by symbolic trajectory evaluation. In: Correct Hardware Design and Verification Methods, Lecture Notes in Computer Science, vol. 2144. Springer, Berlin Heidelberg New York, 1999, pp. 386-402
4. Boigelot, B., Godefroid, P.: Model checking in practice: an analysis of the ACCESS.bus protocol using SPIN. In: Formal Methods Europe, Lecture Notes in Computer Science, vol. 1051. Springer, Berlin Heidelberg New York, 1996, pp. 465-478
5. Camilleri, A.J.: A hybrid approach to verifying liveness in a symmetric multi-processor. In: Theorem-Proving in Higher-Order Logics, Lecture Notes in Computer Science, vol. 1275. Springer, Berlin Heidelberg New York, 1997, pp. 49-67
6. Chou, C.-T.: The mathematical foundation of symbolic trajectory evaluation. In: Computer Aided Verification, CAV, Lecture Notes in Computer Science, vol. 1633. Springer, Berlin Heidelberg New York, 1999, pp. 196-207
7. Clarke, E., Grumberg, O., Hiraishi, H., Jha, S., Long, D., McMillan, K., Ness, L.: Verification of the Futurebus+ cache coherence protocol. Formal Methods Syst Design 6(2): 217-232, 1995
8. Curzon, P.: The importance of proof maintenance and reengi-neering. In: Alves-Foss, J., (ed.), HOL-95: B-track Proc., Sept. 1995, pp. 17-31
9. Dennis, L.A., Collins, G., Norrish, M., Boulton, R., Slind, K., Robinson, G., Gordon, M., Melham, T.: The PROSPER toolkit. In: Tools and Algorithms for Constructing Systems, Lecture Notes in Computer Science, vol. 1785. Springer, Berlin Heidelberg New York, 2000, pp. 78-92
10. Ercegovac, M.D., Lang, T.: Division and square root, digit-recurrence algorithms and implementations. Kluwer, Boston, 1994
11. Gries, D.: The science of programming. Springer, Berlin Heidelberg New York, 1981
12. Hayes, I.: Applying formal verification to software development in industry. In: Hayes, I., (ed.), Specification case studies. Prentice-Hall, Englewood Cliffs, 1987, pp. 285-310
13. Hazelhurst, S., Seger, C.J.H.: Symbolic trajectory evaluation. In: Kropf, T., (ed.), Formal Hardware Verification. Springer, Berlin Heidelberg New York, 1997, pp. 3-78
14. Hinton, G., Sager, D., Upton, M., Boggs, D., Carmean, D., Kyker, A., Roussel, P.: The microarchitecture of the Pentium 4 processor. Intel Technol J, Q1, Feb. 2001
15. IEEE.: IEEE Standard for binary floating-point arithmetic. ANSI/IEEE Std 754-1985, 1985
16. Jones, M., Gopalakrishnan, G.: A PCI formalization and refinement. In: TPHOLs 2000, Supplemental Proc., OGI Technical Report CSE 00-090, 2000, pp. 115-124
17. Jones, R.B., O'Leary, J.W., Seger, C.-J.H., Aagaard, M.D., Melham, T.F.: Practical formal verification in microprocessor design. IEEE Design Test, July 2001, pp. 16-25
18. Kaivola, R., Aagaard, M.D.: Divider circuit verification with model checking and theorem proving. In: Theorem Proving in Higher-Order Logics, Lecture Notes in Computer Science, vol. 1869. Springer, Berlin Heidelberg New York, 2000, pp. 338- 355
19. Kaivola, R., Narasimhan, N.: Multiplier verification with symbolic simulation and theorem proving. In: HLDVT'01, 6th annual IEEE International Workshop on High-level Design Validation and Test. IEEE Computer, New York, 2001, pp. 115-120
20. Kulkarni, S., Rushby, J., Shankar, N.: A case study in component-based mechanical verification of fault-tolerant programs. In: ICDCS Workshop on Self-Stabilizing Systems, 1999, pp. 33-40
21. Mokkedem, A., Leonard, T.: Formal verification of the Alpha 21364 network protocol. In: Theorem Proving in Higher-Order Logics, Lecture Notes in Computer Science, vol. 1869. Springer, Berlin Heidelberg New York, 2000, pp. 443-461
22. Paulson, L.: ML for the Working Programmer. Cambridge, Cambridge, 1996
23. Russinoff, D.M.: A mechanically checked proof of IEEE compliance of the floating point multiplication, division and square root algorithms of the AMD-K7 processor. London Math Soc J Comput Math, 1: 148-200, 1998
24. Seger, C.J.H., Bryant, R.E.: Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods Syst Design, 6(2): 147-189, 1995