Xs are for trajectory evaluation, booleans are for theorem proving

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1703, Issue , 1999, Pages 202-218

  Aagaard, Mark D ^a   Melham, Thomas F ^b   O’Leary, John W ^a  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER CIRCUITS; DESIGN; FORMAL LOGIC; HARDWARE; RECONFIGURABLE HARDWARE; SEMANTICS; THEOREM PROVING; TRAJECTORIES;

DECISION PROCEDURE; HIGHER ORDER LOGIC; MODEL CHECKER; SHALLOW EMBEDDING; SYMBOLIC TRAJECTORY EVALUATION; TEMPORAL OPERATORS;

MODEL CHECKING;

EID: 84896809809     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48153-2_16     Document Type: Conference Paper

References (18)

1. M. D. Aagaard, R. B. Jones, and C.-J. H. Seger. Formal verification using parametric representations of Boolean constraints. In ACM/IEEE Design Automation Conference, July 1999.
2. S. Agerholm and H. Skjødt. Automating a model checker for recursive modal assertions in HOL. Technical Report DAIMI IR-92, Computer Science Department, Aarhus University, 1990.
3. A. Cheng and K. Larsen, editors. Program and Abstracts of the BRICS Autumn School on the Verification, Aug. 1996. BRICS Notes Series NS-96-2.
4. C.-T. Chou. Predicates, temporal logic, and simulations. In C.-J. H. Seger and J. J. Joyce, editors, HOL User’s Group Workshop, pages 310–323. Springer Verlag; New York, Aug. 1994.
5. C.-T. Chou. The mathematical foundation of symbolic trajectory evaluation. In Workshop on Computer-Aided Verification. Springer Verlag; New York, 1999. To appear.
6. G. C. Gopalakrishnan and P. J. Windley, editors. Formal Methods in Computer- Aided Design. Springer Verlag; New York, Nov. 1998.
7. M. J. C. Gordon and T. F. Melham, editors. Introduction to HOL: a theorem proving environment for higher order logic. Cambridge University Press, New York, 1993.
8. S. Hazelhurst and C.-J. H. Seger. Symbolic trajectory evaluation. In T. Kropf, editor, Formal Hardware Verification, chapter 1, pages 3–78. Springer Verlag; New York, 1997.
9. A. J. Hu and M. Y. Vardi, editors. Computer Aided Verification. Springer Verlag; New York, July 1998.
10. J. Joyce and C.-J. Seger. Linking BDD based symbolic evaluation to interactive theorem proving. In ACM/IEEE Design Automation Conference, June 1993.
11. M. Newey and J. Grundy, editors. Theorem Proving in Higher Order Logics. Springer Verlag; New York, Sept. 1998.
12. J. O’Leary, X. Zhao, R. Gerth, and C.-J. H. Seger. Formally verifying IEEE compliance of floating-point hardware. Intel Technical Journal, First Quarter 1999. Online at http://developer.intel.com/technology/itj/.
13. The omega project, 1999. http://www.ags.uni-sb.de/projects/deduktion/.
14. Proof and specification assisted design environments, ESPRIT LTR project 26241, 1999. http://www.dcs.gla.ac.uk/prosper/.
15. S. Rajan, N. Shankar, and M. Srivas. An integration of model checking automated proof checking. In Workshop on Computer-Aided Verification. Springer Verlag; New York, 1996.
16. C.-J. H. Seger and R. E. Bryant. Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design, 6(2):147–189, Mar. 1995.
17. M. Y. Vardi and P. Wolper. Reasoning about infinite computations. Information and Computation, 115:1–37, 1994.
18. J. von Wright. Mechanising the temporal logic of actions in HOL. In M. Archer, J. J. Joyce, K. N. Levit, and P. J. Windley, editors, International Workshop on the HOL Theorem Proving System and its Applications, pages 155–159. IEEE Computer Society Press, Washington D. C., Aug. 1991.