A hybrid approach to verifying liveness in a symmetric multi-processor

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1275, Issue , 1997, Pages 49-67

  Camilleri, Albert J ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL VERIFICATION; MODEL CHECKING; MULTIPROCESSING SYSTEMS;

BUS ARBITRATION; EXISTING SYSTEMS; HEWLETT-PACKARD; HYBRID APPROACH; MULTI PROCESSOR SYSTEMS; MULTI-PROCESSORS; SYMMETRIC MULTI-PROCESSORS; VERIFICATION METHODOLOGY;

THEOREM PROVING;

EID: 84896897196     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0028385     Document Type: Conference Paper

References (10)

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3. Camilleri A., Fleming R., Odineal R., Prekeges D., ‘Formal Verification of Liveness of a Multi-Processor Bus Protocol’, pp. 409-412, Proceedings of the 1993 HP Design Technology Conference, Portland, 25-28 May, 1993. HP Confidential.
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10. McMillan K. L., Schwalbe J., ‘Formal Verification of the Encore Gigamax Cache Consistency Protocol’, in International Symposium on Shared Memory Multiprocessors, 1991.