Performance characterization of TAS-MRAM architectures in presence of capacitive defects

5th International Conference on Advances in System Testing and Validation Lifecycle, VALID 2013, Held at SoftNet 2013

Volumn , Issue , 2013, Pages 39-44

  Azevcdo, Joao ^a   Virazcl, Arnaud ^a   Cheng, Yuenqing ^a   Bosio, Alberto ^a   Dilillo, Lugi ^a   Girard, Patrick ^a   Todri, Aida ^a   Alvarez Hérault, Jérémy ^b  

^a LIRMM   (France)

^b CROCUS Technology   (France)

Author keywords

Capacitive defects; Fault modeling; Non volaitte memories; Spintronics; TAS MRAM; Test

Indexed keywords

EID: 84894851469     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Semiconductor Industry Association, "International technology roadmap for semiconductors (ITRS)," 2011.
2. C.L. Su, C.W. Tsai, C.W. Wu, C.C. Hung, Y.S. Chen, and M.J. Kao, "Testing MRAM for Write Disturbance Fault," in Proc. of IEEE International Test Conference, pp. 277-288,2006.
3. C.L. Su, R.F. Huang, and C.W. Wu, "MRAM Defect Analysis and Fault Modeling," in Proc. of IEEE International Test Conference, pp. 124-133,2004.
4. J, Azevcdo, A. Virazel, A. Bosto, L. Dilillo, P. Girard, A. Todri, G. Prenat, J. Alvarez-Herault, and K, Mackay, "Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures," in Proc. of Design Automation and Test in Europe, pp. 532-537, 2012.
5. J. Azevedo, A. Virazel. A. Bosio, L. Dilillo, P. Girard, A. Todri, G. Prenat, J. Alvarez-Herault, and K, Mackay, "Impact of Resistive-Bridge Defects in TAS-MRAM Architectures." in Proc. of IEEE Asian Test Symposium, 2012.
6. X. Aragones, J.L. Gonzalez, F. Moll, and A. Rubio, "Noise Generation and Coupling Mechanisms in Deep-Submicron lCs," IEEE Design & Test of Computers, vol. 19, no. 5, pp. 27-35, Sept.-Oct. 2002.
7. D.D. Tang and YJ. Lee, "Magnetic Memory-Fundamentals and Technology," Cambridge University Press, uk, 2010.
8. M. El Baraji et at, "Dynamic Compact Model of Thermally Assisted Switching Magnetic Tunnel Junctions," Journal of Applied Physics, vol. 106, no 12,2009.
9. W. Guo, "Compact Modeling of Magnetic Tunnel Junctions and Design of Hybrid CMOS/Magnetic Integrated Circuits," Ph.D. Thesis at Institui Polytechniquc de Grenoble, 2010.
10. Cadence Inc., Spectre, User Guide 2008.