Impact of resistive-open defects on the heat current of TAS-MRAM architectures

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 532-537

  Azevedo, J ^a   Virazel, A ^a   Bosio, A ^a   Dilillo, L ^a   Girard, P ^a   Todri, A ^a   Prenat, G ^b   Alvarez Herault, J ^c   Mackay, K ^c  

^a LIRMM   (France)

^b UMR 8191   (France)

^c Crocus Technology   (France)

Author keywords

fault modeling; heat current; non volatile memories; resistive open defects; spintronics; TAS MRAM; test

Indexed keywords

DEFECTS; MAGNETIC RECORDING; MAGNETIC STORAGE; MEMORY ARCHITECTURE; RANDOM ACCESS STORAGE; SPINTRONICS; TESTING;

ELECTRICAL SIMULATION; EMERGING TECHNOLOGIES; FAULT MODEL; HEAT CURRENTS; MAGNETIC RANDOM ACCESS MEMORY; NON-VOLATILE MEMORY; READ/WRITE OPERATIONS; RESISTIVE-OPEN DEFECTS;

MRAM DEVICES;

EID: 84862082597     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176526     Document Type: Conference Paper

References (16)

1. M.N. Baibich, J.M. Broto, A. Fert, F. Nguyen Van Dau, F. Petroff, "Giant Magneto-resistance of (001)Fe/(001)Cr Magnetic Super-lattices", Phys. Rev. Lett., 61(21):2472-2475, Nov 1988.
2. G. Binasch et al., "Enhanced Magneto-resistance in Layered Magnetic Structures with Anti-ferromagnetic Interlayer Exchange", Phys. Rev. B, 39(7):4828-4830, Mar 1989.
3. Semiconductor Industry Association, "International technology roadmap for semiconductors (ITRS)", 2010.
4. N. Bruchon, "Evaluation, Validation and Design of Hybrid CMOS - non-volatile Emerging Technology Cells for Dynamically Reconfigurable Fine Grain Architecture", Ph.D. Thesis at Université Montpellier II, Dec 2007.
5. C.L. Su, C.W. Tsai, C.W. Wu, C.C. Hung, Y.S. Chen, M.J. Kao, "Testing MRAM for Write Disturbance Fault", International Test Conference, pp. 277-288, 2006.
6. C.L. Su, R.F. Huang, C.W. Wu, "MRAM Defect Analysis and Fault Modeling", International Test Conf., pp. 124-133, 2004.
7. D.D. Tang, Y.J. Lee, "Magnetic Memory - Fundamentals and Technology", Cambridge University Press, UK, 2010.
8. C. Tannous, J. Gieraltowski, "The Stoner-Wohlfarth model of ferromagnetism", Eur. J. Phys., 29, 475, 2008.
9. T.M. Maffitt et al., "Design considerations for mram", IBM J. Res. Dev., 50(1):25-39, 2006, ISSN 0018-8646.
10. L. Savchenko, B. N. Engel, N. D. Rizzo, M. F. D. Herrera, J. A. Janesky, U.S. Patent No. 6,545,906 (Apr. 2003).
11. M. El Baraji et al., "Dynamic Compact Model of Thermally Assisted Switching Magnetic Tunnel Junctions", Journal of Applied Physics, Vol. 106, No 12, 2009.
12. W. Guo, "Compact Modeling of Magnetic Tunnel Junctions and Design of Hybrid CMOS/Magnetic Integrated Circuits", Ph.D. Thesis at Institut Polytechnique de Grenoble, 2010.
13. J. Slonczewski, "Current-driven excitation of magnetic multilayers", Journal of Magnetism and Magnetic Materials, 159:L1-L7, jun 1996.
14. Cadence Inc., Spectre, User Guide 2008.
15. W. Needham, C. Prunty, E.H. Yeoh, "High Volume Microprocessor Test Escapes, An Analysis of Defects Our Tests Are Missing", International Test Conference, pp. 25-34, 1998.
16. A. J. van de Goor and Z. Al-Ars, "Functional Memory Faults: A Formal Notation and a Taxonomy", VLSI Test Symposium, 281-286, 2000.