Testing MRAM for write disturbance fault

Proceedings - International Test Conference

Volumn , Issue , 2006, Pages

  Su, Chin Lung ^a   Tsai, Chih Wea ^a   Wu, Cheng Wen ^a   Hung, Chien Chung ^b   Chen, Young Shying ^b   Kao, Ming Jer ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FAILURE ANALYSIS; FLASH MEMORY; MAGNETIC FIELDS; MICROPROCESSOR CHIPS; ROBUST CONTROL;

DISTURBANCE FAULT; MAGNETIC RANDOM ACCESS MEMORY (MRAM); MAGNETIC TUNNELING JUNCTION (MTJ) DEVICE;

RANDOM ACCESS STORAGE;

EID: 39749200848     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2006.297702     Document Type: Conference Paper

References (26)