Noise generation and coupling mechanisms in deep-submicron ICs

IEEE Design and Test of Computers

Volumn 19, Issue 5, 2002, Pages 27-35

  Aragonès, Xavier ^a   González, Jose Luis ^a   Moll, Francesc ^a   Rubio, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SPURIOUS SIGNAL NOISE;

ON-CHIP NOISE GENERATION; SIMULTANEOUS SWITCHING NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 0036735641     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2002.1033789     Document Type: Article

References (11)

1. Power supply noise analysis methodology for deep-submicron VLSI chip design
2. Delay testing considering power supply noise effects
3. Test generation for ground bounce in internal logic circuitry
4. Vector generation for power supply noise estimation and verification of deep-submicron designs
5. Fault modeling and simulation for crosstalk in system-on-chip interconnects
6. Detectability of spurious signals with limited propagation in combinational circuits
7. Spurious signals in digital CMOS VLSI circuits: A propagation analysis
8. Test generation in VLSI circuits for crosstalk noise
9. Experimental comparison of substrate noise coupling using different wafer types
10. Principles of substrate crosstalk generation in CMOS circuits