Impact of resistive-bridge defects in TAS-MRAM architectures

Proceedings of the Asian Test Symposium

Volumn , Issue , 2012, Pages 125-130

  Azevedo, J ^a   Virazel, A ^a   Bosio, A ^a   Dilillo, L ^a   Girard, P ^a   Todri, A ^a   Prenat, G ^b   Alvarez Herault, J ^c   MacKay, K ^c  

^a LIRMM   (France)

^b CEA GRENOBLE   (France)

^c CROCUS Technology   (France)

Author keywords

Fault modeling; Non volatile memories; Resistive bridge defects; Spintronics; TAS MRAM; Test

Indexed keywords

ELECTRICAL SIMULATION; FAULT MODELING; HIGH INTEGRATION DENSITY; MAGNETIC RANDOM ACCESS MEMORIES; MEMORY TECHNOLOGY; MRAM TECHNOLOGY; MULTIPLE CELLS; NON-VOLATILE MEMORIES; READ/WRITE OPERATIONS; SINGLE CELLS; TAS-MRAM; TEST; TEST ALGORITHMS; WRITE OPERATIONS;

DEFECTS; MAGNETIC STORAGE; MAGNETOELECTRONICS;

MRAM DEVICES;

EID: 84872524154     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2012.37     Document Type: Conference Paper

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