A theoretical approach to estimation of bounds on power consumption in digital multipliers

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 6, 1997, Pages 473-481

  Satyanarayana, Janardhan H ^a,b   Parhi, Keshab K ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Bounds; Low power; Multipliers; Pipelining; Theoretical

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ESTIMATION; MATHEMATICAL MODELS; PIPELINE PROCESSING SYSTEMS; SWITCHING FUNCTIONS;

BAUGH WOOLEY MULTIPLIER; BINARY TREE MULTIPLIER; WALLACE TREE MULTIPLIER;

MULTIPLYING CIRCUITS;

EID: 0031166010     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.592578     Document Type: Article

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