A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 1, 1997, Pages 114-118

  Jou, Shyh Jye ^a   Chen, Chang Yu ^a   Yang, En Chung ^a   Su, Chau Chin ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

Multiplier accumulator; Pipeline arithmetic; Static and dynamic circuits

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MATRIX ALGEBRA; SEMICONDUCTOR DEVICE MODELS; TRANSISTORS;

ADDER CELLS; COMPLEMENTARY PASS TRANSISTOR LOGIC (CPL); MULTIPLIER ACCUMULATOR (MAC);

MULTIPLYING CIRCUITS;

EID: 0030784328     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.553190     Document Type: Article

References (9)

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