Exploring multiplier architecture and layout for low power

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1996, Pages 513-516

  Meier, Pascal C H ^a   Rutenbar, Rob A ^a   Carley, L Richard ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STRUCTURES; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC WIRING; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; OPTIMIZATION; RANDOM PROCESSES; TIMING CIRCUITS; VECTORS;

GATE LEVEL ANALYSES; OPTIMISTIC TIMING; POWER CONSUMING GLITCHING; RANDOM VECTORS; WALLACE TREES;

MULTIPLYING CIRCUITS;

EID: 0029703088     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)