Simulation-based design error diagnosis and correction in combinational digital circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 70-78

  Nayak, Debashis ^a   Walker, D M H ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; DIGITAL CIRCUITS; ERROR CORRECTION; FAILURE ANALYSIS; ITERATIVE METHODS;

COMBINATORIAL DIGITAL CIRCUITS; DESIGN ERROR DIAGNOSIS AND CORRECTION;

INTEGRATED CIRCUIT TESTING;

EID: 0032638330     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (30)