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Volumn , Issue , 2000, Pages 541-544
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Static timing analysis with false paths
a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
FALSE PATHS;
STATIC TIME;
BUFFER STORAGE;
DELAY CIRCUITS;
LOGIC DESIGN;
MATHEMATICAL MODELS;
TIME MEASUREMENT;
DIGITAL CIRCUITS;
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EID: 0033696542
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (4)
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References (3)
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