Linear programming for gate sizing

Closing the Power Gap Between ASIC and Custom: Tools and Techniques for Low Power Design

Volumn , Issue , 2007, Pages 121-149

  Chinnery, David ^a   Keutzer, Kurt ^b  

^a ADVANCED MICRO DEVICES   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84892307816     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-0-387-68953-1_6     Document Type: Chapter

References (26)

1. Berkelaar, M., and Jess, J., "Gate sizing in MOS digital circuits with linear programming," in Proceedings of the European Design Automation Conference, 1990, pp. 217-221.
2. Brglez, F., and Fujiwara, H., "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," in Proceedings of the International Symposium Circuits and Systems, 1985, pp. 695-698.
3. Chandrakasan, A., and Brodersen, R., "Minimizing Power Consumption in Digital CMOS Circuits," in Proceedings of the IEEE, vol. 83, no. 4, April 1995, pp. 498-523.
4. Chinnery, D., Low Power Design Automation, Ph. D. dissertation, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 2006.
5. Dharchoudhury, A., Blaauw, D., Norton, J., Pullela, S., and Dunning, J., "Transistor-level sizing and timing verification of domino circuits in the Power PC microprocessor," in Proceedings of the International Conference on Computer Design, 1997, pp. 143-148.
6. Fishburn, J., and Dunlop, A., "TILOS: A Posynomial Programming Approach to Transistor Sizing," in Proceedings of the International Conference on Computer-Aided Design, 1985, pp. 326-328.
7. Forrest, J., Nuez, D., and Lougee-Heimer, R., CLP User Guide, http://www. coin-or. org/ Clp/userguide/
8. Goering, R., "The battle for logic synthesis," EE Times, September 9, 2004. http:// www. eetimes. com/news/design/columns/tool-talk/ showArticle. jhtml?articleID=46200731
9. Hansen, M., Yalcin, H., Hayes, J., ISCAS High-Level Models. http://www. eecs. umich. edu/ ~jhayes/iscas. restore/benchmark. html
10. Hansen, M., Yalcin, H., Hayes, J., "Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering," IEEE Design & Test of Computers, vol. 16, no. 3, 1999, pp. 72-80.
11. ILOG, ILOG CPLEX 10. 1 User's Manual, July 2006, 476 pp.
12. Jacobs, E., "Speed-Accuracy Trade-off in Gate Sizing," in Proceedings of the workshop on Circuits, Systems and Signal Processing, 1997, pp. 231-238.
13. Kasamsetty, K., Ketkar, M. and Sapatnekar, S., "A New Class of Convex Functions for Delay Modeling and their Application to the Transistor Sizing Problem," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 7, 2000, pp. 779-788.
14. Kulkarni, S., Srivastava, A., and Sylvester, D., "A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems," International Symposium on Low-Power Electronics Design, 2004, pp. 200-205.
15. Nair, R., et al., "Generation of Performance Constraints for Layout," IEEE Transactions on Computer-Aided Design, vol. 8, no. 8, 1989, pp. 860-874.
16. Narendra, S., et al., "Comparative Performance, Leakage Power and Switching Power of Circuits in 150 nm PD-SOI and Bulk Technologies Including Impact of SOI History Effect," Symposium on VLSI Circuits, 2001, pp. 217-8.
17. Nguyen, D., et al., "Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing Optimization," International Symposium on Low Power Electronics and Design, 2003, pp. 158-163.
18. Nikoli?, B., et al., "Layout Decompression Chip for Maskless Lithography," in Emerging Lithographic Technologies VIII, Proceedings of SPIE, vol. 5374, 2004, 8 pp.
19. Pant, P., Roy, R., and Chatterjee, A., "Dual-Threshold Voltage Assignment with Transistor Sizing for Low Power CMOS Circuits," IEEE Transactions on VLSI Systems, vol. 9, no. 2, 2001, pp. 390-394.
20. Satish, N., et al., "Evaluating the Effectiveness of Statistical Gate Sizing for Power Optimization," Department of Electrical Engineering and Computer Science, University of California, Berkeley, California, ERL Memorandum M05/28, August 2005.
21. Sirichotiyakul, S., et al., "Stand-by Power Minimization through Simultaneous Threshold Voltage Selection and Circuit Sizing," in Proceedings of the Design Automation Conference, 1999, pp. 436-41.
22. Srivastava, A., Sylvester, D., and Blaauw, D., "Power Minimization using Simultaneous Gate Sizing Dual-Vdd and Dual-Vth Assignment," in Proceedings of the Design Automation Conference, 2004, pp. 783-787.
23. Synopsys, Design Compiler User Guide, version U-2003. 06, June 2003, 427 pp.
24. Tennakoon, H., and Sechen, C., "Gate Sizing Using Lagrangian Relaxation Combined with a Fast Gradient-Based Pre-Processing Step," in Proceedings of the International Conference on Computer-Aided Design, 2002, pp. 395-402.
25. Wei, L., et al., "Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications," in Proceedings of the Design Automation Conference, 1999, pp. 430-435.
26. Yeo, E., et al., "A 500-Mb/s Soft-Output Viterbi Decoder," IEEE Journal of Solid-State Circuits, vol. 38, no. 7, 2003, pp. 1234-1241.