Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications

IEICE Electronics Express

Volumn 10, Issue 23, 2013, Pages

  Suzuki, Daisuke ^a   Natsui, Masanori ^a   Mochizuki, Akira ^a   Miura, Sadahiko ^b   Honjo, Hiroaki ^b   Kinoshita, Keizo ^a   Sato, Hideo ^a   Ikeda, Shoji ^a   Endoh, Tetsuo ^a   Ohno, Hideo ^a   Hanyu, Takahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

Field programmable gate array; Magnetic tunnel junction device; Nonvolatile logic in memory architecture; Power gating

Indexed keywords

COMPUTER CIRCUITS; FABRICATION; FLIP FLOP CIRCUITS; LOGIC GATES; MAGNETIC DEVICES; MAGNETISM; MEMORY ARCHITECTURE; STATIC RANDOM ACCESS STORAGE; TUNNEL JUNCTIONS;

CIRCUIT CONFIGURATIONS; MAGNETIC TUNNEL JUNCTION; MOTION VECTOR PREDICTION; NON-VOLATILE FLIP-FLOPS; NON-VOLATILE LOGIC; POWER GATINGS; STANDBY-POWER DISSIPATION; TYPICAL APPLICATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84890352209     PISSN: 13492543     EISSN: None     Source Type: Journal    
DOI: 10.1587/elex.10.20130772     Document Type: Article

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