An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 318-319

  Sinangil, Mahmut E ^a   Chandrakasan, Anantha P ^b  

^a NVIDIA   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL-BASED DESIGN; HIERARCHICAL SENSING; MOBILE APPLICATIONS; PROCESSING CAPABILITY; SENSING NETWORKS; SWITCHING ACTIVITIES; TOTAL ENERGY CONSUMPTION; TRANSISTOR LEVEL DESIGN;

CMOS INTEGRATED CIRCUITS; DESIGN; DIGITAL STORAGE; ENERGY EFFICIENCY; ENERGY UTILIZATION; LAPTOP COMPUTERS; PIXELS; STATIC RANDOM ACCESS STORAGE; T-CELLS; VIDEO SIGNAL PROCESSING;

DATA REDUCTION;

EID: 84876580953     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487751     Document Type: Conference Paper

References (6)

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3. H. Fujiwara, et al., "Novel Video Memory Reduces 45% of Bitline power Using Majority Logic and Data-Bit Reordering," IEEE TVLSI, vol. 16, no. 6, pp. 620-627, Jun. 2008
4. I.J. Chang, et al., "A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications," IEEE TCSVT, vol. 21, no. 2, pp. 101-112, Feb. 2011
5. B. Wicht, et al., "Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier," IEEE JSSC, vol. 39, no. 7, pp. 1148-1158, Jul. 2004
6. M.E. Sinangil, et al., "Hardware-Aware Motion Estimation Search Algorithm Development for High-Efficiency Video Coding (HEVC) Standard," 2012 IEEE ICIP, pp. 1529-1532, Sep. 2012